Abstract: A single-pass method for test pattern generation for sequential circuits employs a local-fault at each time-frame. The result is that a fault arriving at circuit primary output lines unambiguously signals the discovery of a valid test pattern sequence for the fault. The valid test pattern sequence is reconstructed from stored history and is used to test a sequential circuit.

Abstract: A single-pass, concurrent validation method for generating test pattern sequences for sequential circuits maps fault objects arriving at circuit next-state lines into good next-state fault objects, and passes these mapped results to a next time-frame by placing the good next-state fault objects on present-state lines corresponding to the next-state lines at which to fault objects arrived. Path-enabling functions created during an initial time-frame are reused for all subsequent time-frames, permitting a fault-propagation size and a path-enabling function size to be bounded by a function size established during the initial time-frame. A valid test pattern sequence is found when a primary output line has a good output level that is a complement of a faulty output level for the line. In one embodiment, the determination and comparison of output levels is carried out concurrently.

Abstract: A method for an incremental behavioral validation of a digital design expressed in a hardware description language includes: receiving a design expressed in HDL code; providing a user interface permitting a designer to insert special comments into the received HDL code; using the special comments to identify testable parts of the design; creating a demonstration sequence for a testable part; performing a behavioral simulation of the testable part and applying the demonstration sequence at inputs of that part to drive the simulation; displaying the results of the simulation via the user interface by observing outputs of the simulated testable part, permitting the designer to determine whether the testable part implements the requirements of an informal specification; modifying the HDL design to correct designer identified failures; and selecting a next testable part and continuing until all testable parts correctly implement the designer's understanding of the informal specification.

Abstract: A single-pass method for generating test patterns for sequential circuits operates upon an iterative array of time-frames representing the circuit. A mapping function is inserted at the end of each time-frame. Fault objects arriving at circuit next-state lines are mapped into good next-state fault objects and are placed onto corresponding present-state lines for a next time-frame. The good next-state mapping permits fault-propagation and path-enabling function size to be bounded by a size established during an initial time-frame. Path-enabling functions created during the initial time-frame are saved and are reused during subsequent time-frames. A search for test patterns continues from one time-frame to a next until a valid test pattern is found for each detectable fault.

Abstract: A method for an incremental behavioral validation of a digital design expressed in a hardware description language includes: receiving a design expressed in HDL code; providing a user interface permitting a designer to insert special comments into the received HDL code; using the special comments to identify testable parts of the design; creating a demonstration sequence for a testable part; performing a behavioral simulation of the testable part and applying the demonstration sequence at inputs of that part to drive the simulation; displaying the results of the simulation via the user interface by observing outputs of the simulated testable part, permitting the designer to determine whether the testable part implements the requirements of an informal specification; modifying the HDL design to correct designer identified failures; and selecting a next testable part and continuing until all testable parts correctly implement the designer's understanding of the informal specification.

Abstract: A method for creating test benches for digital circuit design verification (1) partitions a design for purposes of test bench creation according to circuit type, (2) identifies circuit types and creates packaged testing strategies, (3) uses ATPG techniques to create comprehensive test sequences based on the circuit type classifications, and (4) incorporates the ATPG-produced test stimuli and expected responses into the test bench templates.