Abstract: An analog filter includes a first arithmetic operation section 2-1 having a plurality of sets of processing circuit being cascade connected, each processing circuit having an S/H circuit of plural stages for holding a ??-modulated signal and an analog adder for adding the input and output signals of the S/H circuit, in which the number of stages of the S/H circuits 11-1, 14-1, 17-1 and 20-1 decreases toward the end of cascade connection, and a second arithmetic operation section 2-2 configured in the same way, which are cascade connected. By using such an analog filter, over-sampling and convolution of a ??-modulated signal are conducted so that the envelope of the filter output may be a quadratic curve of finite carrier that converges to zero at finite sampling points to prevent phase distortion of an LPF and a discretization error due to a conventional function.

Abstract: A compressing device comprises plural stages of delay circuits (1-1 to 4-1) and multiplying/adding circuits (5-1 to 10-1) that performs weighted addition of output data from the delay circuits (1-1 to 4-1) according to the value of a digital basic function and thereby determines thinned-out data from sampling data sequentially inputted. Since the thinned-out data is determined by the compression part using a digital basic function serving as the original of a sampling function of infinite supports defferentiable once or more times over the whole range, a compression ratio of at lease 8 can be achieved only by the simple four operations. Further, since interpolation data is determined by the decompression part by using the same digital basic function, the original data before the compression can be reproduced with substantial fidelity by only the simple four operations.

Abstract: With respect to data having periodicity to be compressed, windows of the same size are set for every two sections according to an interval of peaks appearing substantially periodically and processing for sorting sample data alternately among the set windows of the same size is sequentially performed, whereby a frequency of data having periodicity is replaced with an approximately half frequency without damaging reproducibility to original data at all to make it possible to apply compression processing to data of the replaced low frequency. If this sorting processing is applied to compression processing having a characteristic that a compression ratio is not increased in a high-frequency region, it becomes possible to improve a compression ratio without damaging a quality of reproduced data by decompression at all.

Abstract: With respect to data having periodicity to be compressed, windows of the same size are set for every two sections according to an interval of peaks appearing substantially periodically and processing for sorting sample data alternately among the set windows of the same size is sequentially performed, whereby a frequency of data having periodicity is replaced with an approximately half frequency without damaging reproducibility to original data at all to make it possible to apply compression processing to data of the replaced low frequency. If this sorting processing is applied to compression processing having a characteristic that a compression ratio is not increased in a high-frequency region, it becomes possible to improve a compression ratio without damaging a quality of reproduced data by decompression at all.

Abstract: It is object to provide an oversampling circuit and a digital to analog converter capable of realizing a smaller circuit and reducing a cost of parts. The oversampling circuit comprises multiplying section 1, four data holding sections 2-1 through 2-4, four data selectors 3-1 through 3-4, an adding section 4, and two integrating circuits 5-1 and 5-2. Input data is multiplied by four multiplicators by the multiplying section 1, and four multiplication results held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of four step functions outputted from the respective data selectors, and then digital integrating operations corresponding to the sum are carried out by means of two integrating circuits.

Abstract: A sampling function waveform data generating device for fast generating data on a waveform approximating a sampling function with a simple circuit structure. Data on a waveform of a step function is outputted from a memory 20. A first digital integrating circuit 30 integrates the data on waveform of the step function and outputs data on a waveform of a broken-line function. A second digital integrating circuit 40 integrates the data on the waveform of the broken-line function and outputs data on a waveform approximating a sampling function. The outputted sampling function is a function of a local support that is differentiable once, takes on 1 in sampling position t=0, 0 in all the other sampling positions, 0 in the ranges t<−3 and t>+3, and a value other than 0 in the other range, and converges to 0 in sampling positions t=±3.

Abstract: It is object to provide a digital-to-analog converter capable of generating an output waveform having less distortion without increasing the operating speed of components. A D/A converter comprises a multiplying section 1, four data holding sections 2-1 through 2-4, four data selectors 3-1 through 3-4, an adding section 4, a D/A converter 5, and two integrating circuits 6-1 and 6-2. Input data is multiplied by four multiplicators by the multiplying section 1, and the four multiplication results are held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of the step functions outputted from the four data selectors. Furthermore, a stepwise analog voltage corresponding to the sum is generated by the D/A converter 5 and integrated twice by means of the two integrating circuits 6-1 and 6-2.