Abstract: A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O1 and I/O2 of a latch circuit 1 are connected to the drain terminals of MOS transistors M1 and M2 having the same characteristics. Input terminals IN1 and IN2 are provided to the gate and source terminals of the MOS transistor M2, and input terminals IN3 and IN4 are provided to the gate and source terminals of the MOS transistor M2. A bias circuit 2 brings the MOS transistors M1 and M2 into the same bias state. The difference of the input signals supplied to the input terminals IN1 and IN2 is compared with the difference of the input signals supplied to the input terminals IN3 and IN4. Since the comparison result is outputted from the first and second input/output terminals I/O1 and I/O2, the input offset voltage does not affect the differential comparison circuit.

Abstract: A hysteresis comparator circuit and a waveform generating circuit reduce a power consumption of a DC/DC converter so as to improve a power consumption efficiency when the DC/DC converter is operated with a relatively small load. The hysteresis comparator circuit is connected to a reference voltage source providing a reference voltage. A hysteresis comparator compares an input voltage with one of a first threshold voltage and a second threshold voltage. A hysteresis voltage generating circuit selectively generates one of the first and second threshold voltages by controlling a state of electric charge stored in each of the capacitors. An electric charge stored in the capacitors is provided from the reference voltage source.