Abstract: A high-speed multi-write read only memory array includes word lines, select lines, bit lines, and sub-memory arrays. There are a first word line, a first select line, a second select line, a first bit line, a second bit line, a third bit line, and a fourth bit line. Each sub-memory array includes a first memory cell coupled to the first word line, the first select line, and the first bit line, a second memory cell coupled to the first word line, the first select line, and the second bit line, a third memory cell coupled to the first word line, the second select line, and the third bit line, and a fourth memory cell coupled to the first word line, the second select line, and the fourth bit line.

Abstract: A small-area common-voltage multi-write non-volatile memory array includes word lines, select lines, common-voltage lines, and sub-memory arrays. The word lines include a first word line and a second word line. The select lines include a first select line. The common-voltage lines are directly coupled together. The common-voltage lines include a first common-voltage line and a second common-voltage line. Each sub-memory array includes a first non-volatile memory cell coupled to the first word line, the first select line, and the first common-voltage line and a second non-volatile memory cell coupled to the second word line, the first select line, and the second common-voltage line.

Abstract: A multi-write read-only memory array includes word common-source lines, bit lines, and sub-memory arrays. The word common-source lines include a first word common-source line and a second word common-source line. The bit lines include a first bit line and a second bit line. Each sub-memory array includes a first memory cell coupled to the first word common-source line and the first bit line, a second memory cell coupled to the first word common-source line and the second bit line, a third memory cell coupled to the second word common-source line and the second bit line, and a fourth memory cell coupled to the second word common-source line and the first bit line.

Abstract: A small-area common-voltage anti-fuse array includes word lines, select lines, common-voltage lines, and anti-fuse elements. The word lines include a first word line and a second word line. The select lines are perpendicular to the common-voltage lines and the word lines. The select lines include a first select line. The common-voltage lines are directly coupled together. The common-voltage lines include a first common-voltage line and a second common-voltage line. Each anti-fuse element includes a first anti-fuse memory cell coupled to the first word line, the first select line, and the first common-voltage line and a second anti-fuse memory cell coupled to the second word line, the first select line, and the second common-voltage line.

Abstract: A high writing rate antifuse array includes at least one sub-memory array including two antifuse memory cells arranged side by side between two neighboring bit lines. Each of two antifuse memory cells includes an antifuse transistor. The antifuse transistor has at least one sharp corner overlapping an antifuse gate above a first gate dielectric layer. Each of two antifuse memory cells includes a selection transistor. The second gate dielectric layers of two selection transistors are connected with each other. Thus, two antifuse memory cells are connected with the same select line and the same word line but are respectively connected with different bit lines. In the present invention, a common source contact is used, and two selection transistors share a channel, whereby to stabilize the source structure, increase the channel width of the selection transistors, and raise the writing rate without increase of overall area of the layout.

Abstract: A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.

Abstract: A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Abstract: A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.

Abstract: A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array.

Abstract: A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.

Abstract: An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.

Abstract: An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.

Abstract: A method of fast erasing a low-current EEPROM array. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The source or the drain is floated during erasing to perform the fast bytes-erasing with low current, low voltage and low cost.

Abstract: A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.

Abstract: The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. An ion implantation is performed by masking partial regions to prevent the existence of the conventional lightly doped drain (LDD) structure. An undoped region is formed in the semiconductor substrate under the two sides of the first electric-conductive gate, to increase the intensity of electric field between the gate and the substrate or between the gate and the transistor, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM. The present invention applies to the EEPROM with a single gate transistor structure.

Abstract: An erasing method of a single-gate non-volatile memory is provided. The single-gate non-volatile memory has a single floating gate. The erasing method includes applying a voltage to the drain without applying to the gate to create and control an inversion layer. Therefore the required erasing voltage is reduced and the erasing speed is improved to avoid the over-erase problem.

Abstract: The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM, in addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.

Abstract: A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.

Abstract: A non-volatile memory with a single gate-source common terminal and an operation method thereof are provided. The non-volatile memory includes a transistor and a capacitor structure both embedded in a semiconductor substrate. The transistor includes a first dielectric layer, a first electric-conduction gate and several first ion-doped regions. The capacitor structure includes a second dielectric layer, a second electric-conduction gate and a second ion-doped region. The memory may further include a third ion-doped region below the second dielectric layer. The first and second electric-conduction gates are electrically connected to form a single floating gate of the memory cell. The source and second ion-doped region are electrically connected to form a single gate-source common terminal.

Abstract: A method for operating a low-cost EEPROM array is disclosed. The EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line and a second word line. The common source lines include a first common source line. Each sub-memory array includes a first memory cell and a second memory cell, which are respectively connected with the first and second word lines. Each of the first and second memory cells is also connected with the first bit line group and the first common source line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method operates all the operation memory cells and uses special biases to program or erase memory cells massively in a single operation.