Abstract: An apparatus is provided. The apparatus includes: a first substrate including first cooling means using a refrigerant that is circulated with the outside; a second substrate disposed to be in parallel with, and apart from, the first substrate and thus to form first heat accumulation space between the first and second substrates, the second substrate including second cooling means using a refrigerant that is circulated with the outside; a first fan generating a first air flow in the first heat accumulation space in a direction parallel to the first and second substrates; and a housing of a closed structure.

Abstract: The present disclosure according to at least one embodiment provides a semiconductor test apparatus comprising: a failure memory (FM) block storing failure data, which is generated from a result of testing a semiconductor device, a buffer memory (BM) block to/in which the failure data stored in the FM block is copied/stored, and a field programmable gate array (FPGA) performing a first control operation for controlling the FM block and a second control operation for controlling the BM block.

Abstract: A semiconductor test apparatus is provided. The semiconductor test apparatus includes: a test management unit determining a test mode, generating a test signal in accordance with the determined test mode, and transmitting the test signal to fail memories; and one or more fail memory boards including the fail memory, which store fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals, wherein if the determined test mode is a first test mode, at least some of the failure memory boards are powered off.

Abstract: A semiconductor wafer test system for controlling the supply of power to a semiconductor wafer test apparatus is provided. The semiconductor wafer test system includes a test operating server and the semiconductor wafer test apparatus. The test operating server manages a wafer test schedule and allocates lots to a prober, which loads wafers into the semiconductor wafer test apparatus, in accordance with the wafer test schedule. The test operating server sends a mode switch request to the semiconductor wafer test apparatus in accordance with the wafer test schedule, and the semiconductor wafer test apparatus is switched to a waiting mode in response to receipt of a request to switch to the waiting mode from the test operating server, and is switched to a ready mode in response to receipt of a request to switch to the ready mode from the test operating server.