Abstract: A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault processing unit is external and different with respect to said central processing unit and said further fault processing unit comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller. Validation of operations of said central processing unit is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check.
Type:
Grant
Filed:
July 9, 2004
Date of Patent:
December 30, 2008
Assignee:
Yogitech Spa
Inventors:
Riccardo Mariani, Silvano Motto, Monia Chiavacci
Abstract: A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault processing unit is external and different with respect to said central processing unit and said further fault processing unit comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller. Validation of operations of said central processing unit is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check.
Type:
Application
Filed:
July 9, 2004
Publication date:
March 3, 2005
Applicant:
Yogitech Spa
Inventors:
Riccardo Mariani, Silvano Motto, Monia Chiavacci