Patents Assigned to YorChip, Inc.
  • Publication number: 20240320186
    Abstract: An IC, e.g., a bare die, includes an array of bit-slice tiles. Each bit-slice tile has a ground circuit, a supply circuit, an ESD protection circuit, and a bit-transmit circuit and/or bit-receive circuit for a communication protocol, such as UCIe and/or BoW. Bondpads, using an interconnect layer that can be at or near the top of the metal stack, are placed over one or more bit-slice tiles, and can connect with one or more of the circuits in these one or more of the bit-slice tiles. To configure the IC, one selects a communication protocol, bump pitch, and number of data bits. Based on the bump pitch, the number of bit-slice tiles per data bits is determined, and tiles are grouped for each bondpad to be used. In each group, the bondpad is created in a top interconnect layer, and connected with a circuit in a bit-slice in the group.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 26, 2024
    Applicant: YorChip, Inc.
    Inventor: Kashmira JOHAL