Patents Assigned to Yoshitaka Sugawara
  • Patent number: 8786024
    Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 22, 2014
    Assignees: Yoshitaka Sugawara, Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Patent number: 8748937
    Abstract: A semiconductor device includes a semiconductor layer of a first conductor type; a first semiconductor layer of a second conductor type, on the front of the semiconductor layer; a second semiconductor layer of the second conductor type, on the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductor type, on the second semiconductor layer and having a lower impurity concentration than the second semiconductor layer; a first semiconductor region of the first conductor type, in a surface layer of the third semiconductor layer; a second semiconductor region of the second conductor type, in a surface layer of the first semiconductor region; an input electrode contacting the second semiconductor region; a control electrode disposed above part of the first semiconductor region with an insulating film therebetween; and an output electrode disposed on the back of the semiconductor layer.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: June 10, 2014
    Assignees: Fuji Electric Co., Ltd., Yoshitaka Sugawara
    Inventors: Yoshitaka Sugawara, Nobuyuki Takahashi