Abstract: Converting 24 frame per second film source material to 60 fields per second video involves converting one film frame into either two or three video fields using a repeating 3:2 field pattern, referred to as a 3:2 pulldown. When one film frame is made into three video fields, there will be a redundant video field. Once the source material has been transferred to video, the video is edited and distributed. When compressing video that was originally film source, the presence of the duplicate fields results in sub optimal compression. The highest efficiency compression can be achieved when the redundant fields are skipped and the frame rate is returned to that of the original film source. Thus, an inverse 3:2 pulldown, is necessary to identify and remove the redundant video fields before the video is compressed. To identify the redundant video fields, a method and apparatus is disclosed that generates motion vectors and error displacements for adjacent video fields.

Abstract: A novel apparatus for and method of calculating the SAD values for half pixels is disclosed. The invention interpolates, in a serial fashion, half pixel values from full pixels contained in a search window. These half pixels ale then compared with pixels in a template macro block. The differences are then generated and accumulated in registers. The search window and template macro block pixels are shifted into FIFOs whereby a plurality of adders generates half pixel values. Latches are used to store and delay the half pixel values for input to a bank of subtractors. The subtractors calculate the differences between the interpolated half pixels and the template macro block pixels. The output of the subtractors are accumulated resulting in eight SAD values.

Abstract: An apparatus for processing sum of the absolute differences (SAD) is disclosed. A novel circuit is disclosed which eliminates the requirement of taking the absolute value of intermediate partial sum results. The absolute value function is only needed after the final summation stage. Subtraction units take the difference between each pair of values to be processed. The output of the subtraction units are input to a first level of two input summation units. If there is more than one summation unit in the first level, the output of these summation units are input to a second level of summation units. At each level half the number of units are required until a level is reached having only one unit. The absolute value of the last unit is then taken which forms the final SAD result. Each summation unit performs an addition on its two inputs while preserving the magnitude of their sum. Depending on the sign of one of the inputs, the two inputs are either added to each other or subtracted from each other.

Abstract: Video compression systems often use motion compensation to compress the data. Motion compensation systems usually use motion vectors to represent motion. A multipass motion vector determination unit is introduced that makes more then one pass to select a motion vector. The multipass motion vector determination unit first examines an initial search window area around each macroblock to select a first motion vector for each macroblock. The multipass motion vector determination unit then determines a second search window for each macroblock based upon the first motion vector found for that macroblock. Specifically, the second search window consist of an area located in the direction of the first motion vector. A second motion vector is selected from the second search window. Additional motion vectors may similarly be selected.

Abstract: Optimizing the encoding time for a variable length coding unit involves allowing the 8.times.8 blocks to be processed consecutively. Thus, a method and apparatus that allows for efficient processing of the 8.times.8 blocks consecutively is required. A method and apparatus is provided that generates variable length code (VLC) data without requiring buffer memory for storing coefficient data temporarily or special circuitry for generating end-of-block (EOB) Codes. An input code is received. The input code includes an end-of-block (EOB) indicator, a zero run-length, and a coefficient level. The input code is converted into a corresponding VLC and the VLC is output. The input code is converted into the corresponding VLC by: (1) Forming an address based upon the EOB indicator, the zero run-length, and the coefficient level. For example, the EOB indicator may be the most significant bit of the address, followed by the zero run-length, and the least significant portion of the address may be the coefficient level.

Abstract: A method of implementing a fast video encoder by approximating a frame motion vector is introduced. MPEG-2 encoding uses both field and frame vectors in the encoding process. To implement an encoder in an efficient manner, an approximated motion vector created from two field motion vectors is used. The frame motion vector may be determined using the two field motion vectors alone, or by using the two field motion vectors in conjunction with their respective absolute error values. By using the disclosed methods, a motion estimation part for generating frame motion vector is not necessary. Only two field motion estimation parts are required to determine the field motion vectors, the frame motion vector is then approximated using the two field motion vectors. The cost and complexity of a digital video encoder system is thereby reduced.

Abstract: A method and apparatus for efficient motion vector detection is disclosed that provides an expanded search window with a plurality of motion processors. The internal search window of each motion processor is arranged as a set of N row by M column rectangular subblocks. An address generator circuit scans a stream of pixel data values out of a reference frame memory while a set of delay circuits route the stream of pixel data values to the input paths for the internal subblocks and match input timing for the motion processors.