Abstract: A method of and device for automatic gain control (AGC) incorporates digitally controlled variable gain amplifiers (VGAs). An AGC circuit comprises multiple AGC stages, where each of the stages comprises: respective I and Q VGAs; a detector for detecting respective I and Q output signals received from the respective I and Q VGAs; an analogue to digital converter for converting the detected I and Q output signals; and a digital engine for adjusting the respective I and Q VGAs for differences between the detected I and Q output signals and a reference signal. Using staggered AGCs incorporating respective I and Q VGAs splits the total dynamic range between n stages, allowing for reduced gain requirements in the VGAs. Using digital control for setting the VGA gains reduces analogue variations and I/Q gain imbalances. Using multiple update rates or magnitudes in the VGA control improves dynamic settling time.

Abstract: The present invention relates to wireless communications and is particularly applicable to devices and modules for correcting errors introduced to a wireless signal after its transmission. An equalizer is provided which compensates for undesirable effects on received radio signals introduced by either signal processing or by the transmission medium. In operation, the equalizer multiples the complex received signal with a complex corrective signal that compensates for these effects. A tap corrective signal corrects for time-varying channel effects (i.e. channel distortions), a timing tracking signal corrects for carrier frequency offset errors, and a phase tracking signal corrects for sampling frequency offset errors.

Abstract: Systems and methods relating to the provision of gain, phase and delay adjustments to signals to be used by a predistortion subsystem. A portion of an input signal is delayed by delay elements prior to being received by the predistortion subsystem. The delayed input signal portion is also received by a feedback signal processing subsystem that adjusts the gain and phase of the feedback signal based on the delayed input signal portion. The adjusted feedback signal is used, along with the delayed portion of the input signal, to determine an appropriate predistortion modification to be applied to the input signal.

Abstract: Systems, methods and devices for scrambling/descrambling sets of data bits using subsets of a recurring sequence of scrambler bits. A self-synchronous scrambler, regardless of the generating polynomial being implemented, will generate repeating sequences of scrambler bits regardless of the initial stage of the scrambler. To implement a parallel scrambler, given a current state of the scrambler, the next n states of the scrambler are predicted based on the current state of the scrambler. The scrambling operation can then be preformed using the values in the current state—parallel logic operations between preselected bits of the current state will yield the required values to be used in scrambling an incoming parallel data set. Once these required values are generated, a parallel logical operation between the required values and the incoming data set will result in the scrambled output data.

Abstract: Systems and methods related to amplifier systems which use a predistortion subsystem to compensate for expected distortions in the system output signal. A signal processing subsystem receives an input signal and decomposes the input signal into multiple components. Each signal component is received by a predistortion subsystem which applies a predistortion modification to the component. The predistortion modification may be a phase modification, a magnitude modification, or a combination of both and is applied by adjusting the phase of the fragment. The predistorted component is then separately processed by the signal processing subsystem. The processing may take the form of phase modulation and amplification. The phase modulated and amplified components are then recombined to arrive at an amplitude and phase modulated and amplified output signal. The predistortion modification is applied to the components to compensate for distortions introduced in the signal by the signal processing subsystem.

Abstract: We disclose an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. An input module combines a plurality of inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator generates multiplicands. At least two complex multiplier modules perform complex multiplications with at least one of the complex multiplier modules receiving an output from the input module. A map module receives outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs.

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Abstract: Embodiments of the present invention comprise methods and devices for amplifying a signal by amplifying a first signal and by then amplifying a second signal only if the first signal exceeds a predetermined threshold. The first and second amplified signals are then combined, and the combination is fed back to a signal source and used to control the values of the first and second signal. The combination is further transmitted to a load. In the preferred embodiment, the first amplified signal is transmitted through an impedance inverter before it is combined with the second amplified signal.

Abstract: The invention relates to the field of wireless communications, more particularly to a method of and device for switching between antennae in communication with a diversity receiver, each of the antennae receiving signals transmitted from a single source. A packet from a transmitter is received by respective antenna communicating with a diversity receiver. The signal strength of the preamble of the packet received in a first antenna is sampled. If the signal strength is of sufficient magnitude to affect reliable reception, the associated antenna is selected for the duration of the packet transmission. If the signal strength is below a predetermined threshold the signal strength of the preamble of the packet received in a second antenna is sampled and compared to the sample associated with the first antenna. If the magnitude of the second sample is greater, the signal associated with the second antenna is selected.

Abstract: The present invention comprises systems, methods, and devices for detecting the presence of a specified signal type by autocorrelating the signal with a time-delayed copy of itself, by simultaneously crosscorrelating the signal with an expected signal type, and by then comparing the results of the autocorrelation and crosscorrelation to determine whether or not the signal is present and to ascertain its type.

Abstract: Systems, methods, and devices relating to the provision of deliberate predistortion to an input signal to compensate for distortions introduced by an amplifier subsystem. An input signal is received by a signal processing system which includes a predistortion subsystem. The input signal is decomposed and the fragments are then predistorted by the predistortion subsystem by applying a deliberate predistortion to the fragments. The predistorted fragments are then separately processed and recombined to arrive at the system output signal. The predistortion subsystem adaptively adjusts based on characteristics of the system output signal. Also, the predistortion subsystem is equipped with a control system that is state based—the state of the predistortion subsystem is dependent upon the prevailing conditions and, when required, the control system switches the state of the predistortion subsystem.

Abstract: The present invention relates to wireless communications and is particularly applicable to devices and modules for correcting errors introduced to a wireless signal after its transmission. An equalizer is provided which compensates for undesirable effects on received radio signals introduced by either signal processing or by the transmission medium. In operation, the equalizer multiples the complex received signal with a complex corrective signal that compensates for these effects. A tap corrective signal corrects for time-varying channel effects (i.e. channel distortions), a timing tracking signal corrects for carrier frequency offset errors, and a phase tracking signal corrects for sampling frequency offset errors.

Abstract: Methods and devices for encoding in parallel a set of data bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encoded in parallel using the second subset. The first subset is also encoded in parallel using a subset of an immediately preceding set of data bits. Parallel encoding is realized by using an encoding module utilizing multiple single bit submodule. Each submodule receives a single bit from the first subset and either the second subset or the subset of the immediately preceding data set. Each single bit submodule produces a pair of output bits from the convolutional encoding of a single bit of the first subset and either the second subset or the subset of the immediately preceding data set. The multiple single bit submodules operate in parallel to simultaneously and collectively produce a set of data bits.

Abstract: The invention relates to the field of wireless communications, more particularly to a method of and device for switching between antennae in communication with a diversity receiver, each of the antennae receiving signals transmitted from a single source. A packet from a transmitter is received by respective antenna communicating with a diversity receiver. The signal strength of the preamble of the packet received in a first antenna is sampled. If the signal strength is of sufficient magnitude to affect reliable reception, the associated antenna is selected for the duration of the packet transmission. If the signal strength is below a predetermined threshold the signal strength of the preamble of the packet received in a second antenna is sampled and compared to the sample associated with the first antenna. If the magnitude of the second sample is greater, the signal associated with the second antenna is selected.

Abstract: Improved methods and systems for amplifying a signal are provided. Specifically, systems and methods for amplifying a signal through a lossy switch element tied to two or more voltage sources are provided. In the preferred embodiment, envelope information from the signal is used to smoothly transition between the two or more voltage sources to provide signal amplification over an increased range.

Abstract: The present invention comprises systems, methods, and devices for detecting the presence of a specified signal type by autocorrelating the signal with a time-delayed copy of itself, by simultaneously crosscorrelating the signal with an expected signal type, and by then comparing the results of the autocorrelation and crosscorrelation to determine whether or not the signal is present and to ascertain its type.

Abstract: The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die.

Abstract: The present invention discloses an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. For performing an N-point FFT/IFFT operation in N clock cycles, the optimal hardware implementation consists of several modules. An input module receives a plurality of inputs in parallel and combines the inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator is used to provide multiplicands to the system. At least two complex multiplier modules for performing complex multiplications are required with at least one of the complex multiplier modules receiving an output from the input module. Each of the complex multiplier modules receives multiplicands from the at least one multiplicand generator. Furthermore, at least one of the complex multiplier modules receives an output of another complex multiplier module.

Abstract: Systems and methods relating to the provision of gain, phase and delay adjustments to signals to be used by a predistortion subsystem. A portion of an input signal is delayed by delay elements prior to being received by the predistortion subsystem. The delayed input signal portion is also received by a feedback signal processing subsystem that adjusts the gain and phase of the feedback signal based on the delayed input signal portion. The adjusted feedback signal is used, along with the delayed portion of the input signal, to determine an appropriate predistortion modification to be applied to the input signal.

Abstract: Methods and devices for encoding in parallel a set of data. bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encoded in parallel using the second subset. The first subset is also encoded in parallel using a subset of an immediately preceding set of data bits. Parallel encoding is realized by using an encoding module utilizing multiple single bit submodule. Each submodule receives a single bit from the first subset and either the second subset or the subset of the immediately preceding data set. Each single bit submodule produces a pair of output bits from the convolutional encoding of a single bit of the first subset and either the second subset or the subset of the immediately preceding data set. The multiple single bit submodules operate in parallel to simultaneously and collectively produce a set of data bits.