Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract: A balun that includes a first conductor, a second conductor and a third conductor. The first conductor has a length of about one quarter wavelength of a selected center frequency. The first conductor also has a first end connected to a first balanced power amplifier output port. The second conductor has a length of about one quarter wavelength of the selected center frequency. The second conductor also includes a first end connected to a second balanced power amplifier output port and a second end connected a second end of the first conductor. The third conductor has a length of about one quarter wavelength of the selected center frequency. The third conductor has a first end connected to an antenna port and a second end connected to a ground potential.

Abstract: A balun that includes a first conductor, a second conductor and a third conductor. The first conductor has a first length. The first conductor also has a first end connected to a first balanced power amplifier output port. The second conductor has substantially the same first length. The second conductor also includes a first end connected to a second balanced power amplifier output port and a second end connected a second end of the first conductor. The third conductor has substantially the same first length. The third conductor has a first end connected to an antenna port and a second end connected to a ground potential.

Abstract: A system and method for compensating a parasitic capacitance on a differential amplifier output includes a first differential output and a second differential output of the differential amplifier. The first differential output coupled to the second differential output by a first conductor that has a length of about one half wavelength. The first and the second differential outputs have a parasitic capacitance that can be measured. A second conductor is coupled to the first differential output. The second conductor having a length that is less than or equal to about one quarter wavelength and has an inductive reactance that offsets a capacitive reactance of the parasitic capacitance.

Abstract: In wireless communications such as in the Bluetooth communication system, an execution unit sequentially receives software instructions for execution. Prior to completing each instruction, the execution unit issues an interrupt indicating the upcoming completion of the instruction execution and awaits receipt of the next instruction. A Link Manager issues limited instructions, and a Link Controller includes a hardware execution unit for executing the limited instructions. A processing unit in the Link Manager performs remaining functions under control of a software program.

Abstract: A hold cell implementing a closed-loop, common mode negative feedback method is provided. The hold cell enables generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the hold cell is used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal is used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the hold cell in a low power oscillator is fully implementable in a CMOS process.

Abstract: Disclosed is a frequency conversion circuit with sideband suppression in which a first mixer receives an in-phase signal (IFi) and is driven by a local oscillator having an in-phase (0°) oscillator signal (LOi), and produces two sideband signals (LO+IF, LO−IF). A second mixer receives a quadrature phase frequency signal (IFq+) and is driven by a local oscillator having a quadrature (180°) oscillator signal (LOq), and produces two sideband signals (LO+IFq, LO−IFq). One of the sidebands from the second mixer is 180° out of phase with respect to the same sideband from the first mixer. A signal combiner then receives and combines the two sidebands from the first mixer and the two sidebands from the second mixer, the signal combiner suppressing one sideband and enhancing the other sideband. In preferred embodiments, the mixers comprise MOSFET transistors and the signal combiner comprises capacitive elements.

Abstract: Methods and apparatus for buffering RF signals. A method includes receiving an input signal, wherein the input signal alternates between a first polarity and a second polarity. From the input signal, a first current is generated, wherein the first current is proportional to the input signal when the input signal has the first polarity, and approximately equal to zero when the input signal has the second polarity, and a second current is generated, wherein the second current is proportional to the input signal when the input signal has the second polarity, and approximately equal to zero when the input signal has the first polarity. A third current is generated proportional to the first current, and a fourth current is generated proportional to the second current. The first and fourth currents are applied to a first terminal of an inductor; and the second and third currents are applied to a second terminal of the inductor.

Abstract: Methods and apparatus of amplifying signals. One method includes receiving a variable power supply, generating a variable bias current, and applying the bias current to a load such that an average output voltage is generated. The method further includes receiving an input signal, generating a current proportional to the input signal, and subtracting the current from the variable bias current. As the variable power supply changes value by a first amount, the variable bias current is varied such that the average output voltage varies by the first amount.

Abstract: An analog memory cell that may be incorporated into a low power oscillator is provided. The analog memory cell stores an analog voltage as a digital signal and converts the digital signal back to an analog voltage to allow continued generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the analog memory cell in the low power oscillator is fully implementable in a CMOS process.

Abstract: A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed between selected first and second metallic interconnections which are separated by an insulating intermetallic oxide layer. A first metal-dielectric-metal layer capacitor is created over and with a portion of the first metallic interconnection and a second metal-dielectric-metal layer capacitor is created under and with a portion of the second metallic interconnection. A first metal via through the insulating intermetallic oxide layer connects the first metal-dielectric-metal layer capacitor and the second metal-dielectric-metal layer capacitor to form a first terminal of the capacitor structure and a second metal via through the insulating intermetallic oxide layer connects the first metallic interconnection portion and the second metallic interconnection portion to form a second terminal of the capacitor structure.

Abstract: A package for semiconductor devices, and methods for making the same are provided. The package includes a low temperature co-fired ceramic body that has a plurality of conductive interconnect layers. The low temperature co-fired ceramic body includes at least one solder ball attach side. A plurality of solder ball attach pads are defined on the solder ball attach side(s) of the low temperature co-fired ceramic body. Each of the solder ball attach pads is in contact with a conductive via that is in electrical communication with at least one of the plurality of conductive interconnect layers, and each solder ball attach pad has metallic content that is limited to silver.

Abstract: An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Abstract: Disclosed is a CMOS transistor amplifier for small RF signals which operates in a Class AB mode. The serially connected P channel and N channel transistors of the CMOS transistor pair have DC bias voltages applied to the control gates, and the small input signal is capacitively coupled to the gates of the CMOS transistor pair. In a preferred embodiment, the DC voltage bias for the P channel transistor is derived from a second P channel transistor which is approximately identical to the first P channel transistor in structure with the second P channel transistor serially connected with the current source and the voltage at the gate/drain of the transistor resistively coupled to the gate of the first P channel transistor.

Abstract: Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate.

Abstract: Embodiments of the present invention provide flip-chip bond pad arrangements that lead to a smaller increase in die size than conventional approaches. This is accomplished by using the core side of a periphery I/O pad ring for placing some of the bond pads in order to meet the bond pad pitch requirements of flip chip technology. For example, alternating bond pads are moved inward to the core side of the I/O pads or drivers, to meet the bond pad pitch requirement between the bond pads that are moved to the core side as well the bond pads that remain outside of the core. Because the bond pads are moved inward instead of outward, the increase in the die size from the edge of the I/O pad ring is reduced. In an alternative embodiment, the bond pads are each bonded on top of an active circuitry of a corresponding I/O pad.

Abstract: An apparatus for maintaining synchronization with a plurality of asynchronous communication links includes a first counter that generates a first local network clock, and a second counter that generates a second local network clock. The apparatus also includes an offset controller coupled with the first counter and coupled with the second counter, the offset controller configured to load a current network clock value of a first network clock of a first communication link into the first counter, and to load a current network clock value of a second network clock of a second communication link into the second counter. The apparatus further includes a drift controller coupled with the first counter and with the second counter, the drift controller configured to correct a drift between the first local network clock and the first network clock and to correct a drift between the second local network clock and the second network clock.

Abstract: A crystal oscillator circuit includes a crystal driven by a variable current source having a transconductance device with transconductance dependent on current, and a CMOS buffer circuit for receiving a sinusoidal signal from the crystal and providing a square wave output signal. The buffer circuit includes first and second bi-level buffers capacitively coupled to receive sinusoidal signals and operating in a push-pull mode for providing square wave output signals from each of said first and second buffers, and a third buffer driven by output signals from the first and second buffers, whereby duty cycle of the first and second buffers is controlled by bias voltages applied to CMOS transistors in the buffers.