Abstract: A test system for testing high density printed circuit boards with large numbers of integrated circuits. The system is especially suited for testing large scale integrated circuits. The overall test system comprises two principal parts: a cabinet supporting a large number of driver/receiver printed circuit boards and a test fixture supporting a printed circuit board under test. The test fixture connects to the cabinet by a number of pull-down fingers automatically operated by an electromechanical means. Two large arrays of electrical contacts are precisely mated together by the operation of the pull-down fingers. When a printed circuit board of a different layout is required to be tested, the test fixture is exchanged for a test fixture wired in conjunction with the new layout.

Abstract: A printed circuit board test fixture has both a vacuum chamber and a bed of nails. Holes through the body of the test fixture coincide with test points on the circuit board to be tested. The ends of spring-loaded probes in some of the holes protrude from the surface of the test fixture to form the bed of nails. Each end lines up with an associated test node on the printed circuit board. An external vacuum source evacuates air from the vacuum chamber within the test fixture, thus evacuating air from beneath the printed circuit board. The printed circuit board is thus pulled against the bed of nails, the test probe ends contacting the test nodes on the printed circuit board.

Abstract: A digital in-circuit tester has a test-head controller which controls bursts of test vectors generated by a group of driver-receiver channels, the group of driver-receiver channels responsive to an erase instruction from test-head controller. At least one driver-receiver channel is adapted for nullifying the action of an erase instruction. The driver-receiver channel has a first memory for storing information which determines certain actions of the channel during the next burst of test vectors. The memory is responsive to the erase instruction for being erased.

Abstract: A method of detecting possibly electrically-open connections between circuit nodes and pins of components physically connected to the nodes. The pins include input pins and output pins, the input pins connected to corresponding input nodes and the output pins connected to corresponding output nodes. The method comprises the steps of determining if the connections between the input pins and the input nodes can be tested, and then testing for an electrically-open connection between each input pin and its corresponding input node. The two-step method of determining if the connections between the input pins and the input nodes can be tested includes a first step of determining if the output nodes exhibit activity in response to application of stimuli to the input nodes, and continuing testing if there is activity. The second step is determining if each output node exhibits a signature repeated identically in response to stimuli repeated identically at all the input nodes.

Abstract: A circuit board is guided into the correct position over the testing location of a test fixture by means of at least one guide located outside and near to the circumference of the testing location. The surface of the guide which faces the testing location is sloped outwards and upwards, the guide preferably being conical in shape. In test fixtures provided with tooling guide pins which fit through tooling holes on the circuit board for the purpose of accurate positioning over the test location, the lower part of the guide to approximately the same height as the pins is cylindrical, the upper part of the guide being conical.

Abstract: A printed circuit board "bed-of-nails" test fixture, of the type in which the circuit board is moved into electrical contact with the test probes, is provided with a means of ensuring accurate registration between the test probes and the corresponding test nodes on the board when contact is made. This registration is achieved by allowing the support surrounding the circuit board to bend by a hinge mechanism on all four sides, as the circuit board travels towards the probes. The substantially equal opposed forces on opposite edges of the board prevent lateral movement of the board during travel and thus ensure accurate registration.

Abstract: A circuit for use in an in-circuit digital tester for generating data bus and control line test signals to test the electrical performance properties of components in a circuit under test is disclosed. Certain components in a circuit under test, such as microprocessors, are bus oriented devices which perform their functions in predetermined cycles. These cycles have been divided up into control sequences of control signals. Sequences of data signals are also generated. Each test pin in the bed of nails test fixture has a digital test signal generator associated therewith. The present invention operates to program each test signal generator with digital test signal generating data to produce the control and data sequences required to test a device under test during a test cycle. These predetermined sequences in control and data sequences are specified by a sequence in starting addresses of the programmable memory locations containing the selected control and data sequences to be generated.

Abstract: A circuit adapted for use in a high speed computer controlled digital in-circuit tester for obtaining high pulse fidelity at each electrical node of a circuit under test is provided. High pulse fidelity is obtained by minimizing the current in the power supply and digital test signal current loops for the components of the circuit under test. The tester includes a plurality of programmed memory digital test-signal generators responsive to the computer for generating and supplying to the nodes of the circuit under test a complex sequence of digital logic signals. The circuit also includes a plurality of distributed programmable power sources, each power source associated with at least one of said test signal generators, for generating the power supply voltages for the components.

Abstract: A circuit for use in an in-circuit digital tester for generating data bus and control line test signals to test the electrical performance properties of components in a circuit under test is disclosed. Certain components in a circuit under test, such as microprocessors, are bus oriented devices which perform their functions in predetermined cycles. These cycles have been divided up into control signals and data bus signals. Each sequence of control signals are referred to as a protocol sequence. Each test pin in the bed of nails test fixture has a digital test signal generator associated therewith. The present invention operates to program each test signal generator with digital test signal generating data to produce each protocol sequence of the device under test. Test cycles are then run in which a predetermined sequence of protocol sequences are generated to test the device.

Abstract: An apparatus for the automatic, in-circuit testing of the electrical properties of complex digital integrated circuit assemblies is disclosed. A programmed processor is provided to control a set of selectable switches, which connect selected nodes of a circuit under test to certain ones of a plurality of signal lines. One of the signal lines supplies a selected digital test signal from a set of selectable test signals to the selected node. The set of test signals including a Gray code. Another of the signal lines provides a response line connecting a selected node to a functional tester that performs one of a selectable number of intermediate functional tests. One of the functional tests is a signature analysis of the digital response signal in accordance with a cyclic redundancy check (CRC) coding technique.

Abstract: A method and apparatus for automatic, programmed, in-circuit testing of individual logic elements. A plurality of program-operated device connection switches are provided for making connections to the circuit under test. A plurality of program-operated drive circuits are provided for driving nodes of the logic element under test with controlled current, voltage and power to logical 1, logical 0, or a high impedence state. A measurement unit measures an output from the logic element under test. Testing programs are run in a program-controlled processor. The programs have subroutines which correlate with individual types of logic elements. Each logic element is examined, in circuit, independently of neighboring logic elements. A translation memory stores data for translating node addresses to facilitate topology independent subroutine processing of identical elements.

Abstract: A method and apparatus for the high-speed testing of capacitors. A computing amplifier is connected with the capacitor under test to form an integrator which integrates a known excitation signal. The integration is initiated with no charge stored by the capacitor and at a zero crossing of the excitation signal. The integration occurs over a period which produces the maximum voltage across the capacitor. A peak detector measures the maximum voltage across the capacitor to produce a peak detection voltage inversely proportional to the value of the capacitor and directly proportional to a predetermined nominal value of the capacitor. The reciprocal of the output from the peak detector is formed to provide a measurement directly proportional to the capacitor value and inversely proportional to the nominal value of the capacitor.

Abstract: A method and apparatus for automatic, programmed, in-circuit component testing and functional testing. A multi-mode measurement unit having an exciter circuit, computing circuit, and a converter circuit is provided for measuring electrical signals. The measurement unit is controlled by a program-commanded measurement unit controller. A plurality of device connection switches are provided for connecting, by a program-commanded switch controller, the computing circuit to selected nodes of a circuit under test. The switch controller and the measurement unit controller receive commands from a programmed processor which executes stored programs of instruction. The programs contain subroutines which correlate with commanded measurement parameters and sequences within the measurement unit.

Abstract: An apparatus for the automatic, in-circuit testing of the electrical properties of complex digital integrated circuit assemblies is disclosed. A programmed processor is provided to control a set of selectable switches, which connect selected nodes of a circuit under test to certain ones of a plurality of signal lines. One of the signal lines supplies a selected digital test signal from a set of selectable test signals to the selected node. The set of test signals including a Gray code. Another of the signal lines provides a response line connecting a selected node to a functional tester that performs one of a selectable number of intermediate functional tests. One of the functional tests is a signature analysis of the digital response signal in accordance with a cyclic redundancy check (CRC) coding technique.