Abstract: A hybrid analog/digital STB includes a tuner supplying respective analog and digital television signal processing paths. The analog processing path provides demodulated composite analog video and audio signals and the digital processing path provides demodulated component digital video and audio signals. The demodulated analog and video signals are combined in composite or component form to achieve various desirable effects in a highly flexible system architecture. OSD and display map normalization functions are also integrated within the system architecture.

Abstract: A convolutional interleaver or deinterleaver comprises an address signal generator for repeatedly generating [(B-1)N/2]+1 sequences of address signals, where B is a desired interleave depth and N is a value equal to or greater than the number of data bytes in a R-S block of the data stream. Each of the sequences corresponds to a respective row of a B column matrix, the first column of which comprises [(B-1)N/2]+1 consecutively numbered values. Each remaining column comprises the preceding column rotated by an integer multiple of N/B. The address signals are applied to a memory having [(B-1)N/2]+1 storage locations for reading the data stored at the address memory location and then writing the current data byte to the same memory location.

Abstract: An AGC circuit for a digital receiver that receives a digital television signal or the like, including a pilot, and formatted in a plurality of repetitive data segments, each data segment comprising a fixed number of multilevel symbols occurring at a constant symbol rate. The multilevel symbols are converted to corresponding digital values and the pilot (represented by a DC offset) is removed from the digital values. Every fourth symbol is sampled and the samples are accumulated and divided to derive an average symbol value. The average symbol value is compared with a reference average symbol value and the result of the comparison is an AGC potential that controls the tuner and IF gains. A cable/terrestrial input alters the sampling for cable signals to compensate for high level sweep testing in cable systems.

Abstract: A television receiver has a main, or regular, display; a picture-in-picture display; and an on-screen menu display for adjusting various television operating parameters, including those which are channel or source related, such as channel labeling, source labeling and on-screen program guide operation. When a channel or source related menu is displayed for operation on channel or source related functions, the channel or source operated upon is displayed in the picture-in-picture display and the main display may be blanked to present a more legible background for the menu.

Abstract: Upstream transmissions in a two-way communications network are effected from subscriber terminals in upstream packets having one of a plurality of different separately acknowledgeable acknowledgment tags. Downstream acknowledgments of upstream messages are contained in CA packets multiplexed with product packets to form a transport bitstream. The transport bitstream is applied to a digital conditional access module (DCAM) in the terminal which is controlled by the conditional access data bits of the CA packets. The DCAM includes a status register for storing the acknowledgment bits of the CA packets, which bits are coupled by a microprocessor for controlling the upstream transmitter.

Abstract: A method of operating a cable system having premium channel encoders and dedicated smart pay per view encoders, each associated with an individual channel. The pay per view encoders are provided with the addresses of certain subscriber stations that have been approved to decode pay per view events on the associated channels. These certain subscriber stations are addressed on a priority basis by the pay per view encoder handling the pay per view event to set their authorization memories to decode the pay per view event. The authorization memories are updated by RAM groups of five program tags. All of the PPV encoders are assigned to the same RAM group so that in updating authorization memories, the authorization of a subscriber station memory for another pay per view event is not altered. The authorization process is rapidly accomplished and is repeated for a period of time after commencement of the pay per view event.

Abstract: A television signal transmission system comprises a multiplexer for combining a compressed video data signal and one or more auxiliary data signals to form a multiplexed signal for transmission over a channel of fixed bandwidth. The multiplexer is controlled to vary the ratio of the components comprising the multiplexed signal to insure satisfactory reproducible image quality in response to the received compressed video data signal. The compressed video data signal may be buffered prior to combination with the auxiliary data, in which case the multiplexer is also further controlled to vary the ratio of the components comprising the multiplexed signal to maintain the fullness of the buffer at an acceptable level.

Abstract: An HDTV receiver for restricting playback of HDTV signals encrypted with a level 1 encryption. The receiver includes an output port and an input port between which an external, controllable level 1 decryption apparatus is connected. The receiver includes a level 2 encryption circuit coupled to the output port and a level 2 decryption circuit coupled to the input port. The level 1 external decryption apparatus may be controllable from a cable head end, a smart card or a built-in algorithm to control the number of playbacks of recorded level 1 encrypted HDTV signals.

Abstract: A cable transmission system transmits television signals in a family of M-level symbol data constellations. Lower frequency ones of the television signals are transmitted in data constellations of relatively higher values of M and higher frequency ones of the television signals are transmitted in data constellations of relatively lower values of M to optimize signal to noise performance and spectrum utilization.

Abstract: A low phase noise, high frequency low voltage integrated circuit oscillator has a minimum number of live pins. It includes a three transistor current mirror defining a voltage node and a current node with an emitter follower transistor coupled between the voltage node and the current node. An output is taken from the emitter follower transistor and a tuned circuit is coupled to the voltage node. A pair of power supply pins are provided for power application to the integrated circuit and one live pin is coupled to the voltage node. A tuning circuit for affecting capacitance changes for varying the frequency of the oscillator is connectable to the voltage node. In some versions of the oscillator that use a separate crystal, additional pins are needed.

Abstract: A digital data processing system receives compressed variable length encoded digital data in the form of variable length codewords in contiguous variable speed Blocks of data. The boundary signals between adjacent codewords are determined and a demultiplexer sequentially sorts the serial digital data among a plurality of parallelly connected buffers for reducing the bit read speed of the buffers. A corresponding plurality of variable length decoders decodes the data from the buffers and outputs the data in parallel form to a multiplexer where it is reassembled into a serial expanded data stream. The incoming data includes selector information in fixed length headers that are separated, buffered and variable length decoded for controlling the demultiplexer. In one aspect of the invention, the data is sorted into substantially equal sized groups of integral codewords for equalizing the loading of the parallel buffers.

Abstract: A double conversion type television tuning system for a digital television signal includes a synthesizer for developing a tuning voltage for the upconverter. The synthesizer provides bandswitching for dividing the tuning range into four portions and includes a separate local oscillator for each portion. Each local oscillator is enabled by a transistor that is switched by a bandswitch voltage. The output of each oscillator is applied through respective bandswitched buffer amplifiers to an arrangement of three 3 dB hybrid couplers to convey the appropriate local oscillator signal to the upconverter mixer. The system minimizes phase noise and jitter which is essential when operating with digital signals.

Abstract: A digital television signal includes data sent as multilevel symbols in successive data segments each including a synchronizing sync character. The detected synchronizing sync character produces a characteristic having two opposite polarity levels separated by a zero reference level, with the levels occurring at successive sampling points of the television signal, and a detection signal that has a peak occurring in time coincidence with the zero reference level. The detection signal controls sampling of the received television signal. The gain of the received signal is controlled by an AGC circuit that also responds to the detection signal.

Abstract: A television receiver includes a microprocessor, a switched mode power supply and a storage capacitor. The storage capacitor supplies standby power to the microprocessor when the television receiver is off and the switched mode power supply is disabled. While the television receiver is off, the microprocessor monitors the capacitor voltage and turns on the switched mode power supply to recharge the capacitor when its voltage level falls to a predetermined minimum. The microprocessor turns off the switched mode power supply when the capacitor voltage indicates that the capacitor has been recharged.

Abstract: A receiver for receiving transmitted digital signals including either two level or four level symbols that are interleaved in a predetermined pattern in a frame format consisting of a plurality of successive data segments. The symbols are converted into ten bit numbers that are soft sliced to generate four bit numbers representing ranges of values within which each ten bit number may fall. The data represented by the four bit numbers is deinterleaved, a birate flag is generated that identifies the nature of each four bit number, i.e. whether it represents a two level symbol or a four level symbol, and a hard slicer operates, in response to the birate flag, for converting each of the four bit numbers to corresponding two bit binary outputs.

Abstract: A synchronous demodulator is controlled by a phase locked loop for tuning to a pilot in a television signal. A start-up interval is commenced upon initiation of tuning (either after power-up or a channel change) during which a substitute signal at the pilot frequency is supplied to the phase locked loop to rapidly bring the VCO close to its lock-up frequency. Thereafter the IF signal is supplied. The start-up interval is defined by an AFC Defeat signal from a microprocessor and controls an IF switch. The substitute signal is from a crystal oscillator.

Abstract: A synchronizing signal front end processor for video monitors includes a synchronizing signal subprocessor which responds to computer generated horizontal and vertical rate scan signals to provide alternative scan signal coupling in the event of interruption or abnormalities of the applied scan signals. The processor also includes horizontal and vertical synchronizing signal subprocessors which produce output signals indicative of the polarity and frequency of the applied selected scan synchronizing signals. In addition, the vertical and horizontal sync subprocessors provide respective sync out of range signals during sync interruption or abnormality which are utilized to stabilize the monitor display scanning process while switching to alternative scan synchronizing signal sources.

Abstract: A first mixer block converts received MMDS channel frequencies to MMDS frequencies capable of being processed by an MMDS decoder. The MMDS decoder, which includes a crystal controlled reference generator, is located in a benign environment. The reference is supplied to a phase locked loop for controlling a fixed frequency local oscillator that supplies the first mixer. The local oscillator output is also supplied to a second mixer that produces a response signal, of a different frequency, by biphase shift key modulation of said reference that is transmitted back to the transmitting site via the antenna. A squelch circuit precludes transmission of the unmodulated reference.

Abstract: A geometry correction waveform synthesizer includes a plurality of DC controlled multipliers each coupled to respective sources of complimentary geometry correction signals. The DC controlled multipliers are coupled to respective gain control voltage sources as well as null adjustment voltage sources to provide a variable amplitude and polarity correction signal output. The individual correction signal outputs of the DC controlled multipliers are combined to form a composite geometry correction signal which is applied to a gain control circuit. The individual gain control signals used by the DC controlled multipliers are added to form a combined gain control signal which is used to control the composite correction signal amplitude and maintain correction signal amplitude within a predetermined range. An overall gain control couples the composite geometry correction signal to the scan system.

Abstract: An audio power amplifier includes a stacked pair of complementary transistors having the emitters commonly coupled to a load. A driver stage couples the bases of the stacked pair to a source of audio frequency signal. A bootstrap capacitor is coupled between the commonly coupled output node and the supply voltage. An isolation diode is interposed between the bootstrap capacitor and the operating supply to prevent discharge of the bootstrap capacitor into the operating supply during positive signal swings.