Abstract: A field contains a map, a number of E-VSB data segments, and a number of VSB data segments. The map indicates at least the number of E-VSB data segments in the field. The E-VSB data segments are located in the field such that the spacing between the E-VSB segments comprises only x and x+1, where x is dependent on the number of E-VSB data segments in the field as indicated by the map.

Abstract: Frames comprise odd fields and even fields. The frame sync segments of the odd fields contains a current map specifying the location of data in frames, a next map specifying the location of data in a future frame, and a frame count designating the future frame. The frame sync segments of the even field may contain the same information. Alternatively, the frame sync segments of the odd fields contain the current map and part of the frame count, and the frame sync segments of the corresponding even fields contain the next map and the rest of the frame count. A receiver uses the map and frame count information to find data in the fields of received frames.

Abstract: An equalizer that processes blocks of data includes a first finite filter which applies first finite filter coefficients to the blocks of data and a first post-processor which applies first post-processor coefficients to an output of the first finite filter. Ghosts of the blocks of data are not eliminated as a result of the application of the first finite filter coefficients and the first post-processor coefficients. The equalizer also includes a second finite filter which applies second finite filter coefficients to the blocks of data, and a second post-processor which applies second post-processor coefficients to an output of the second finite filter. Ghosts of the blocks of data are not eliminated as a result of the application of the second finite filter coefficients and the second post-processor coefficients. However, an adder adds outputs from the first and second post-processors so that ghosts of the blocks of data are eliminated from an output of the adder.

Abstract: An equalizer applies a window function to input blocks of data. A first finite filter multiplies each of the windowed input blocks of data with a first set of finite filter coefficients to provide respective first adjusted output blocks of data. This multiplication does not result in a full solution to ghosts. A second finite filter multiplies each of the windowed input blocks of data with a second set of finite filter coefficients to provide respective second adjusted output blocks of data. This multiplication also does not result in a full solution to ghosts. An adder performs an addition based upon corresponding ones of the first and second adjusted output blocks of data. A controller controls the window function and the first and second sets of equalizer coefficients so that, as a result of the addition, a substantially full solution to ghosts is obtained.

Abstract: A system supplies a compressed digital signal to a digital television receiver and includes a source of compressed baseband signal. An encoder encodes the baseband signal in a digital format, and the baseband signal has a frequency. The frequency of the encoded baseband signal is shifted by a first frequency shifter. A first interpolator interpolates an output of the first frequency shifter, a second interpolator that interpolates an output of the first interpolator, and a third interpolator that interpolates an output of the second interpolator. A second frequency shifter shifts a frequency of an output of the third interpolator to produce a signal at a selected channel.

Abstract: An iterative decoding system has a first decoder that decodes coded data and a first weighting circuit that reduces channel effects in the coded data based upon a reliability that the first decoder accurately decoded the encoded data. The first weighting circuit produces improved coded data. A second decoder of the iterative decoding system decodes the improved coded data, and a second weighting circuit additionally reduces channel effects in the improved coded data based upon a reliability that the second decoder accurately decoded the improved encoded data.

Abstract: An equalizer substantially eliminates a ghost of a received main signal by (i) applying coefficients b (where b may be equal to one) to the received main signal and the ghost in order to modulate the received main signal and the ghost so that the received main signal and the ghost are unequal, (ii) applying coefficients a to the modulated received main signal and ghost in order to substantially eliminate the ghost, and (iii) applying coefficients c as a window function to the substantially ghost-free received main signal in order to remove the modulation imposed on the received main signal by the coefficients b.

Abstract: A controller controls the automatic positioning of an antenna. The controller is arranged to position the antenna dependent upon a channel selected by a user, a location of a receiver tuned to the selected channel, and a location of a source of a signal associated with the selected channel.

Abstract: A receiver for VSB signals includes tuner channel changing circuitry. AGC circuitry, an IF FPLL and confidence counters, for indicating when signal acquisition or loss occurs. When a loss of signal indication is generated, the IF FPLL is reset, but not the tuner channel changing circuitry and the AGC circuitry, in order to quickly reacquire the signal. If the loss of signal indication persists for a predetermined time or for a predetermined number of loss of signal indications, the IF FPLL, the tuner channel changing circuitry and the AGC circuitry are all reset to reacquire the signal.

Abstract: A transmitter transmits, and a receiver receives, a data frame is transmitted into an 8 MHZ channel. The data frame contains a plurality of data segments, where each of the data segments contain DS symbols. The DS symbols include data symbols, priming symbols, and segment synchronization symbols. The transmitter trellis encodes the data symbols, priming symbols, and segment synchronization symbols. The receiver trellis decodes the data symbols, priming symbols, and segment synchronization symbols. The data frame also contains a mode control ID which the receiver uses in trellis decoding the data symbols, priming symbols, and segment synchronization symbols.

Abstract: A single balanced downconverter includes an insulated substrate with a primary circuit and a secondary circuit, each consisting of an open annular foil element, located on opposite sides of the substrate in juxtaposition with each other and having mutual coupling. A pair of mixing diodes is connected across the ends of the secondary element, which has its center connected to ground. A 2nd local oscillator signal is applied to the primary circuit. A 1st IF signal is applied to, and a 2nd IF signal is developed from, the secondary circuit.

Abstract: Received frame and field coded DCT coefficient blocks are downconverted to lower resolution reconstructed pixel field blocks so that, for example, HDTV programs can be played on NTSC receivers. The frame and field coded DCT coefficient blocks have motion vectors associated therewith. Specifically, the received frame coded DCT coefficient blocks are converted to converted field coded DCT coefficient blocks and an IDCT module is performed on the converted field coded DCT coefficient blocks to produce downconverted field residual or pixel blocks. Also, an IDCT is performed directly on the received field coded DCT coefficient blocks to produce downconverted field residual or pixel blocks. Reference pixel blocks are selected based upon the motion vectors, the reference pixel blocks are upsampled, and the upsampled reference pixel blocks are downsampled.

Abstract: A television receiver system for a healthcare environment where the television receiver has provision for connection of a pendant control mechanism that houses a single switch for controlling the television receiver ON/OFF and tuning functions in a sequential manner and may also contain a pillow speaker and a volume control. The receiver tuning system comprises a cyclical sequence of individual positions for receiving television channels, radio signals and instructional channels, and a position for turning the television receiver OFF. Any position may be designated as the ON position to which the system tunes whenever it is activated, with the OFF position being designated as the position immediately below the ON position.

Abstract: An RF A/B switch associated with a receiver has first and second inputs and an output. A first diode circuit includes a plurality of diodes and an impedance network coupled between the first input and the output. A second diode circuit includes a plurality of diodes and an impedance network coupled between the second input and the output. A controller establishes a common series biasing current through at least one of the diodes in each of the first and second diode circuits. The common series biasing current biases one of the first and second diode circuits so as to configure a respective one of the impedance networks in a low pass filter configuration that couples a signal on one of the first and second inputs to the output, and the common series biasing current biases the other of the first and second diode circuits in a blocking configuration so as to block a signal on the other of the first and second inputs from the output.

Abstract: A dual path equalizer for processing blocks of data includes first and second pre-processors, first and second finite filters, first and second post-processors, and an adder. The first pre-processor applies coefficients b1 to a received signal, the first finite filter applies coefficients a1 to an output of the first pre-processor in order to substantially eliminate a ghost from the received signal, and the first post-processor applies coefficients c1 to an output of the first finite filter. The second pre-processor applies coefficients b2 to the received signal, the second finite filter applies coefficients a2 to an output of the second pre-processor in order to substantially eliminate a ghost from the received signal, and the second post-processor applies coefficients c2 to an output of the second finite filter.

Abstract: Circuits for removing clock related artifacts in an offset QAM generated VSB signal includes a transmitter arrangement and a receiver arrangement. In the transmitter, a detector detects the artifacts and a correlator determines whether the artifacts repeat over two symbols or over four symbols. A signal indicative of the artifacts is used to control processing circuits for adjusting the ratios and levels of the I and Q signal components of the QAM signal for substantially eliminating the artifacts. In the receiver, the received VSB signal is divided into four parallel signals. Each parallel signal is processed to develop an average symbol level that is subtracted before the parallel signals are recombined. The four symbol repeat rate artifacts reflect a DC offset of the VSB signal symbols, which are both positive-going and negative-going and which therefore average to zero for random signals. Averaging is done over N symbols where N is a power of 2.

Abstract: A portable data storage device receives data from a digital broadcast signal receiver that is adapted to separate the data from a digital broadcast signal. The portable data storage device includes a first transceiver that communicates with a second transceiver associated with the digital broadcast signal receiver and further includes a memory for storing the received data. A processor disposed within the portable data storage device controls the storage of the data and further causes a data request signal to be generated and transmitted to the digital broadcast signal receiver. A controller disposed within the digital broadcast signal receiver responds to the data request signal by causing the data separated from the digital broadcast signal to be transmitted via the second transceiver to the portable data storage device. The portable data storage device further includes a data communication port for transferring the data to a personal computer.

Abstract: An MPEG encoded interlaced high definition video stream is decoded and down converted to lower resolution by an MPEG decoder with a reduced amount of reference picture memory. Received frame and field DCT coded blocks are down converted to reconstructed pixel field blocks by first converting the received frame DCT coded blocks to converted field DCT coded blocks. A vertical IDCT and a horizontal IDCT are then performed on the received field DCT coded blocks and on the converted field DCT coded blocks in order to produce residual and pixel field blocks as appropriate. The vertical IDCT is an N point vertical IDCT, and the horizontal IDCT is an M point horizontal IDCT, where N corresponds to the original block size, and where N>M. The residual and pixel field blocks are spatially filtered and down sampled vertically. IDCT, filtering, and down sampling operations are efficiently combined into single linear operators.

Abstract: A transmitter transmits, and a receiver receives, a data frame is transmitted into an 8 MHZ channel. The data frame contains a plurality of data segments, where each of the data segments contain DS symbols. The DS symbols include data symbols, priming symbols, and segment synchronization symbols. The transmitter trellis encodes the data symbols, priming symbols, and segment synchronization symbols. The receiver trellis decodes the data symbols, priming symbols, and segment synchronization symbols. The data frame also contains a mode control ID which the receiver uses in trellis decoding the data symbols, priming symbols, and segment synchronization symbols.

Abstract: A device for provisioning, retrieving, and using data guide information transmitted in a digital broadcast signal is disclosed. A receiver receives the digital broadcast signal which includes digital television programming packets multiplexed with data packets and thereafter routes the received signal to a demodulator. The demodulator provides a demodulated signal to a detector which identifies data packets contained therein. A processor then determines the types of data in the data packets, as well as the respective channels on which the identified types of data are transmitted. The processor prepares a menu for a display screen enabling a user to select the channel of interest, and enables the user to be connected accordingly.