Patents Assigned to ZENO Semiconductor, Inc.
  • Patent number: 10553281
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: February 4, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10553683
    Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 4, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja, Zvi Or-Bach, Dinesh Maheshwari
  • Patent number: 10546860
    Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: January 28, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 10529424
    Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: January 7, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10529853
    Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: January 7, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Dinesh Maheshwari, Yuniarto Widjaja
  • Patent number: 10522213
    Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 31, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 10515968
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 24, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10504585
    Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: December 10, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10497443
    Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 3, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10468102
    Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: November 5, 2019
    Assignee: Zeno Semiconductor, Inc
    Inventor: Yuniarto Widjaja
  • Patent number: 10461084
    Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: October 29, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10461083
    Abstract: A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 29, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 10453847
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 22, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10403361
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 3, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10388378
    Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: August 20, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10373685
    Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 6, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 10354718
    Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja
  • Patent number: 10347636
    Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 9, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10340006
    Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 2, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10340276
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 2, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach