Patents Assigned to ZERO-ERROR SYSTEMS PTE LTD
  • Patent number: 11177807
    Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 16, 2021
    Assignee: ZERO-ERROR SYSTEMS PTE LTD
    Inventors: Joseph Sylvester Chang, Kwen Siong Chong, Ne Kyaw Zwa Lwin, Sivaramakrishnan Hariharakrishnan
  • Patent number: 10930646
    Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes forming a first electrical device having a first region of a first conductivity type, forming a second electrical device having a second region of a second conductivity type, and electrically coupling the first region and the second region to each other, wherein one of the first and second regions is arranged to at least substantially surround the other of the first and second regions. According to further embodiments of the present invention, a method of forming a circuit is also provided.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 23, 2021
    Assignee: ZERO-ERROR SYSTEMS PTE LTD
    Inventors: Joseph Sylvester Chang, Kwen Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Sivaramakrishnan Hariharakrishnan