Patents Assigned to ZeroG Wireless, Inc.
  • Publication number: 20100148831
    Abstract: A buffer circuit is described for buffering signals between a circuit element and a load. The buffer includes a main transistor and a cascode transistor, as well as a distribution line for transferring signals over a distance between the circuit element and the load. The buffer is arranged in a remote cascode topology such that the cascode transistor is located substantially adjacent to the load and remote from the main transistor. The distribution line transfers signals over the distance from the main transistor to the cascode transistor. This remote cascode topology makes it possible to significantly reduce the power consumption of the buffer—as compared to conventional buffers—while maintaining the maximum bandwidth possible.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 17, 2010
    Applicant: ZEROG WIRELESS, INC.
    Inventors: Stanley Bo-Ting Wang, Honglei Wu, Thomas Lee
  • Publication number: 20090296853
    Abstract: A transmitter architecture and method of modulation that include a rotation-direction control circuit for varying the direction of rotation of phase transitions of a phase modulation based on the occurrence of a predetermined pattern of input data. This variation of rotation direction by the rotation-direction control circuit maintains the output spectrum of a modulated signal within the spectral mask requirements of an associated communications standard and thereby enables the use of non-linear power amplifiers in applications that generally require linear amplifiers.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventors: Meng-Chang Doong, Jia-Yi Chen, Thomas Lee
  • Publication number: 20090278517
    Abstract: A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulator 400 receives an input voltage on VIN from a battery or some other power supply at node VIN and supplies a stable regulated voltage to load device 404 at node VOUT. Load device 404 pulls different amounts of current and requires different degrees of tolerance on the voltage at VOUT depending upon its operating conditions. Data collection and control circuit 401 is capable of enabling and disabling regulator 402 and regulator 403. Data collection and control circuit 401 is also capable of measuring certain performance parameters associated with load device 404 and the operating conditions of load device 404. Data collection and control circuit 401 enables regulator 402 if said operating conditions are such that when data collection and control circuit 401 enables regulator 403 the performance parameters associated with load 404 are below a predefined standard.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 12, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventor: Bendik Kleveland
  • Patent number: 7603244
    Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: October 13, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventors: Stanley Wang, Bendik Kleveland, Thomas H. Lee
  • Patent number: 7583211
    Abstract: An analog-to-digital conversion circuit and a method for calibrating an analog-to-digital conversion circuit are provided. A digital translation of an analog voltage is analyzed to determine a characteristic value of the analog voltage. A reference voltage, with which the digital translation is generated, is set to a value that is a minimum amount greater than the characteristic value. Additional embodiments include setting an offset voltage, with which the digital translation is also generated.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: September 1, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventor: Honglei Wu
  • Publication number: 20090206894
    Abstract: A phase-locked loop capable of being dynamically configured to optimize phase-noise performance during different modes of operation. The phase-locked loop may include a switchable charge pump, loop filter and voltage-controlled oscillator having auxiliary circuit components that may be switched in and out to achieve calibration settings for optimizing phase-noise performance for different modes of operation, while minimizing unnecessary power consumption, and without disturbing the stability of the phase-locked loop.
    Type: Application
    Filed: February 17, 2008
    Publication date: August 20, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventors: Stanley Bo-Ting Wang, Meng-Chang Doong
  • Publication number: 20090207824
    Abstract: A wireless (such as Wi-Fi or similar) access point is included in or attached to a device, such as a cellular phone, WiMAX device, other mobile device, etc. One or more wireless units wirelessly access a communication network (and in some cases the Internet) through the wireless access point device. Additionally, such a wireless access point device can receive a transmission from a wireless tag that has been attached to an object to be monitored and can forward information from the wireless tag to a target device along with location information.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 20, 2009
    Applicant: ZeroG Wireless, Inc.
    Inventors: Thomas H. Lee, Michael Palladino, Bendik Kleveland, Vinay Malekal
  • Publication number: 20090201185
    Abstract: An analog-to-digital conversion circuit and a method for calibrating an analog-to-digital conversion circuit are provided. A digital translation of an analog voltage is analyzed to determine a characteristic value of the analog voltage. A reference voltage, with which the digital translation is generated, is set to a value that is a minimum amount greater than the characteristic value. Additional embodiments include setting an offset voltage, with which the digital translation is also generated.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventor: Honglei Wu
  • Publication number: 20090195946
    Abstract: In one embodiment of the present invention, an electrostatic discharge protection circuit provides efficient electrostatic discharge protection to an RFIC. The circuit includes several parts such as an inductor coupled from a first rail to an internal node. A power amplifier transistor having a transconductance control node is coupled to internal circuitry, a first terminal coupled to a second rail, and a second terminal coupled to an internal node. The circuit also comprises a pad coupled to an internal node, and this pad is capable of being coupled to off chip systems such as an antenna. The power amplifier transistor serves as the active device for an RF power amplifier. The inductor serves as one of either a bias inductor or a tank inductor for the RF power amplifier. Additionally the inductor acts as a low impedance path to the first rail to protect the power amplifier transistor during an ESD pulse.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 6, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventor: Bendik Kleveland
  • Publication number: 20090195307
    Abstract: An amplifier circuit and method for amplifying a signal efficiently over a plurality of power ranges. The amplifier circuit including a strong amplifier which is efficient over a first power range and a weak amplifier which is efficient over a second power range. An impedance transformation circuit is used for generating a higher potential and providing increased efficiency when the second range of power is present. A circuit biases active the strong amplifier when the first power range of is present and biases active the weak amplifier when the second power range is present.
    Type: Application
    Filed: February 2, 2008
    Publication date: August 6, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventors: Susan Luschas, Thomas H. Lee
  • Patent number: 7570035
    Abstract: A voltage regulator circuit and method are provided for regulating a voltage accurately in response to rapid variations in the regulator's load. The voltage regulator utilizes a hybrid loop; an embodiment of such utilization is exemplified by circuit 300. Amplifier 301 controls the current flowing through pass element 303 from an unregulated input voltage node Vin to a regulated voltage output node Vout. The regulated output voltage is provided to load 311 so that the voltage across the load stays constant regardless of variations in the current it pulls. The value of the regulated voltage is set by feedback network 302 and the input voltage at node Vref. The regulator feedback loop formed by amplifier 301, pass element 303, and feedback network 302 regulate the voltage at Vout in response to low frequency perturbations in load 311. In response to high frequency perturbations, a sensing network triggers control circuitry 310. Such a sensing network is exemplified in this embodiment by comparators 308 and 309.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: August 4, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventor: Bendik Kleveland
  • Patent number: 7564707
    Abstract: An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: July 21, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventor: Bendik Kleveland
  • Patent number: 7560983
    Abstract: An amplifier circuit and method for amplifying a signal efficiently over a plurality of power ranges. The amplifier circuit including a strong amplifier which is efficient over a first power range and a weak amplifier which is efficient over a second power range. An impedance transformation circuit is used for generating a higher potential and providing increased efficiency when the second range of power is present. A circuit biases active the strong amplifier when the first power range of is present and biases active the weak amplifier when the second power range is present.
    Type: Grant
    Filed: February 2, 2008
    Date of Patent: July 14, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventors: Susan Luschas, Thomas H. Lee
  • Patent number: 7548040
    Abstract: This disclosure relates to wireless battery charging of electronic devices such as wireless headsets/headphones. In one embodiment, an electronic device is provided comprising a speaker comprising a coil, and the coil is operative both to cause the speaker to produce sound and to receive energy transferred to the coil via inductive coupling. The received energy is used to recharge a rechargeable battery in the electronic device. In other embodiments, the coil used to receive the energy that recharges the battery is received by a coil other than the coil in the speaker.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: June 16, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventors: Thomas H. Lee, Arthur J. Collmeyer, Dickson T. Wong
  • Patent number: 7532077
    Abstract: A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: May 12, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventors: Stanley Wang, Thomas H. Lee
  • Publication number: 20090119444
    Abstract: The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block 201 is utilized in tandem with directly accessible fully configurable memory block 207. Arbiter 206 implements the redundant addressing that enables the multiple write cycle NVM functionality. Each block of less configurable memory contains an address segment 203 and a data segment 204. Address segment 203 refers to a specific cell in directly accessible memory 209.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Applicant: ZeroG Wireless, Inc., Delaware Corporation
    Inventor: Paul G. Davis
  • Publication number: 20090054004
    Abstract: A biasing scheme for compensating for a difference in biasing currents between a first circuit element (10) and second circuit element (32) in a stacked circuit configuration. A current-difference source (38) generates a difference current that is substantially equal to the difference between the biasing currents of the first circuit element (10) and second circuit element (32) in order to compensate for process, temperature and supply variations.
    Type: Application
    Filed: August 20, 2007
    Publication date: February 26, 2009
    Applicant: ZeroG Wireless, Inc., Delaware Corporation
    Inventors: Yuen Hui Chee, Thomas H. Lee
  • Publication number: 20090052099
    Abstract: A hybrid circuit (42) for use with communications transceivers. The hybrid circuit (42) combines the function of an ESD protection circuit (12) with the function of a TX/RX switch (10). The input node of the hybrid circuit (42) is connecting between the source of an ESD event (60) and a device to be protected (44). The hybrid circuit (42) includes an ESD protection element (50), which is triggered by a triggering transistor (52). The gate of the triggering transistor (52) is connected to a driver (54) for turning the triggering transistor (52) on during transmission and for turning the triggering transistor (52) off during reception.
    Type: Application
    Filed: August 20, 2007
    Publication date: February 26, 2009
    Applicant: ZeroG Wireless, Inc.
    Inventors: Yuen Hui Chee, Thomas H. Lee, Bendik Kleveland
  • Publication number: 20090043957
    Abstract: A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuit 200 is comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexer 201 to Read Only Memory (ROM) 202. As a result the data in the data location in ROM 202 that corresponds to the requested address will be output to data bus 205. If data locations in ROM 202 become defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuit 200 is programmed with direct addresses to be replaced in ROM 202. The direct addresses are paired to emulation addresses of data locations in configurable memory 203. Upgraded or substitute data is programmed into the configurable memory 203 at the paired emulation address.
    Type: Application
    Filed: March 5, 2008
    Publication date: February 12, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventor: Paul G. Davis
  • Publication number: 20090033298
    Abstract: A voltage regulator circuit and method are provided for regulating a voltage accurately in response to rapid variations in the regulator's load. The voltage regulator utilizes a hybrid loop; an embodiment of such utilization is exemplified by circuit 300. Amplifier 301 controls the current flowing through pass element 303 from an unregulated input voltage node Vin to a regulated voltage output node Vout. The regulated output voltage is provided to load 311 so that the voltage across the load stays constant regardless of variations in the current it pulls. The value of the regulated voltage is set by feedback network 302 and the input voltage at node Vref. The regulator feedback loop formed by amplifier 301, pass element 303, and feedback network 302 regulate the voltage at Vout in response to low frequency perturbations in load 311. In response to high frequency perturbations, a sensing network triggers control circuitry 310. Such a sensing network is exemplified in this embodiment by comparators 308 and 309.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 5, 2009
    Applicant: ZeroG Wireless, Inc.
    Inventor: Bendik Kleveland