Abstract: According to one embodiment, a circuit is disclosed. The circuit comprises a solid state power amplifying device, an input impedance matching circuit and an output impedance matching circuit coupled to the solid state amplifying device. The input impedance matching circuit includes an input pitchfork trace pattern. The output impedance matching circuit includes an output pitchfork trace pattern. The circuit further discloses an input bias circuit and an output bias circuit.
Type:
Grant
Filed:
June 8, 2000
Date of Patent:
March 4, 2003
Assignee:
Zeta, division of Sierra Tech Inc.
Inventors:
Douglas M. Macheel, Peter B. Jones, Lee B. Max