Abstract: When a charging voltage Vs of a charging capacitor C is judged to exceed a voltage Vth1 through a comparator 8 of a charging voltage monitoring circuit 2, a logical output of the comparator 8 becomes "High" so that a control circuit 3 permits a transistor 4 of a discharging circuit 1 to be conductive, whereby the capacitor C discharges. Through such discharging, the charging voltage Vs decreases. When the voltage Vs is then judged to be less than a voltage Vth2, the logical output of the comparator 8 becomes "Low" so that the control circuit 3 stops the operation of the discharging circuit 1, whereby a power IC 18 permits the capacitor C to charge again. The charging and the discharging operation of the capacitor C are repeatedly conducted in this manner that.