Abstract: Described are methods and apparatuses pertaining to stacked integrated circuits having application in ultra-low-power and small form factor design, with fast prototyping and mass-production cycle time, including application for millimeter wave radio frequency circuits.

Abstract: Described is a method comprising a processing, an establishing, and/or a determining. In the processing, an inputted capabilities list including one or more hardware design capabilities may be processed. In the establishing, one or more candidate components for the one or more hardware design capabilities may be established. In the determining, a set of unique candidate netlists capable of satisfying the one or more hardware design capabilities may be determined, the set of unique candidate netlists being based upon the set of candidate components.

Abstract: Described is a packaged component having a first surface and an opposite second surface. The packaged component may comprise a first element a second element, and a third element. The first element may have a first surface and an opposite second surface. The second element may have a first surface and an opposite second surface. The third element may electrically connect a portion of the first element to a portion of the second element. The second surface of the first element may be adjacent to the second surface of the packaged component, and the second surface of the second element may be adjacent to the second surface of the packaged component.

Abstract: Described is an apparatus comprising a semiconductor interconnect substrate and an interface. The semiconductor interconnect substrate may be electrically coupled to one or more components mounted thereon. The interface may be operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode.

Abstract: Described is a method comprising a processing, an establishing, and/or a determining. In the processing, an inputted capabilities list including one or more hardware design capabilities may be processed. In the establishing, one or more candidate components for the one or more hardware design capabilities may be established. In the determining, a set of unique candidate netlists capable of satisfying the one or more hardware design capabilities may be determined, the set of unique candidate netlists being based upon the set of candidate components.

Abstract: A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.

Abstract: A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.