Abstract: A power supply device for supplying power to a server and a power supply management system are provided. The device includes: a power supply control chip, a first connector, a voltage comparator, a counter and a resistance regulation circuit. The resistance regulation circuit includes a pull-up resistance circuit and a pull-down resistance circuit including multiple resistor branches and switches. An input terminal of the voltage comparator is connected to an address input terminal, the other input terminal of the voltage comparator is connected to a connection point of the resistance regulation circuit. An input terminal of the counter is connected to an output terminal of the voltage comparator, each output terminal of the counter is connected to one switch and controls a state of the switch. Each output terminal of the counter is connected to one address pin of the power supply control chip.

Abstract: A design method for displaying a DRC in a classification manner in a PCB design is provided. The design method includes: acquiring layer information contained in a current design, adding the acquired layer information to a DRC Layer menu in a pop up window, acquiring a DRC Type contained in the current design and adding the processed DRC Type to a DRC Type menu in the pop up window after processing the acquired DRC Type; creating an updating function, to update a DRC Type menu list in response to an input action of a user; acquiring an attribute of each item in a DRC Layer menu list and the DRC Type menu list, and inserting the acquired attribute into the updated DRC Layer menu list and the updated DRC Type menu list, to form a feature parameter list.

Abstract: A mainboard and a server are provided. The mainboard includes: a board body, a preset number of Purley platform central processors, and one or more memories. The preset number of Purley platform central processors and the one or more memories are installed on the board body. The Purley platform central processors are sequentially connected with each other, and each of the memories is connected to one of the Purley platform central processors. Each of the memories is configured to receive to-be-burned data inputted from outside and transmit the to-be-burned data to the Purley platform central processor connected with the memory. Each of the Purley platform central processors is configured to burn the to-be-burned data when receiving the to-be-burned data transmitted by the connected memory connected with the Purley platform central processor, to have a function corresponding to the to-be-burned data.

Abstract: A direct current voltage step-down regulation circuit structure is provided, which includes a switching circuit and a feedback regulation circuit connected to the switching circuit. An output capacitor is arranged at an output end of the switching circuit, and the switching circuit receives an input voltage at an input end thereof. The feedback regulation circuit includes a first operational amplifier, a second operational amplifier and voltage division power supplies. A non-inverting input terminal of the first operational amplifier is connected to a first voltage division circuit. A non-inverting input terminal of the second operational amplifier is connected to a second voltage division circuit. The voltage division power supplies are respectively connected to the first voltage division circuit and the second voltage division circuit.

Abstract: A system for improving a switching efficiency of a double network card NCSI management system is provided. The system includes an NCSI Switch which is a two-to-one data strobe device. The NCSI Switch includes three groups of data links A, B, and C. The group A of NCSI data is linked to a controller with an NCSI function, i.e., a BMC MAC module. The group B of data is linked to an onboard network card end, and the group C of data is linked to an external network card slot. The NCSI Switch further includes a Select pin connected to an in-position detection pin of the external network card slot via a logic conversion circuit.

Abstract: A support frame includes a column, a rocker arm, a tray, an adjustment shaft and a fixing block. The column is vertically arranged, the rocker arm is horizontally arranged, and the column and the rocker arm are connected by a hinge. The rocker arm includes a transverse support tube connected to the hinge, and the adjustment shaft is arranged inside the transverse support tube. An elastic member has one end connected to the adjustment shaft and another end connected to the column or the hinge. The transverse support tube is provided with multiple U-shaped grooves, and the fixing block is arranged outside the transverse support tube, and the tray is connected to the fixing block. The fixing block passes through the U-shaped groove to be connected to the adjustment shaft; or, a screw passes through the U-shaped groove, to connect the fixing block to the adjustment shaft.

Abstract: A design method and a packaging method for a PCB board to avoid patch element tombstone, and a PCB board are provided. The method includes: providing at least one patch element placement area on a PCB board, providing pads in each patch element placement area, where each pad group includes two pads, and the two pads are arranged side by side; establishing pad limit areas around the pads; and reflow soldering the patch element to the PCB board. With the above method, the tombstone phenomenon of the patch element can be effectively prevented, the design efficiency is improved, the workload of manual operation of the engineer is reduced, and an error rate is reduced.

Abstract: A layout routing structure and a layout routing method for improving an SI performance of a signal are provided. Each of two positive and negative differential traces on a PCB includes multiple segments D1, multiple segments D2 and multiple segments D3. In each of the two differential traces, the segment D1 and the segment D2 are staggered and parallel to each other, the segment D2 is routed between any two segments D1, and any two adjacent segments D1 and D2 are connected by the segment D3. In one of the two differential traces, all of the segments D1 are routed on the glass cloth, and all of the segments D2 are routed on the epoxy resin. In the other of the two differential traces, all of the segments D1 are routed on the epoxy resin, and all of the segments D2 are routed on the glass cloth.

Abstract: A method for simulating signal integrity of a hybrid model is provided, which includes: establishing a transient simulation link including a front-end chip model, a pre-link model and a terminating impedance model, where the front-end chip model is a Spice model; inputting an ideal step signal to a port reserved in the front-end chip model, and extracting step response data in a steady state; inputting the step response data to an input end of a channel simulation link, where the channel simulation link includes a relay chip model, a post-link model and a back-end chip model, and each of the relay chip model and the back-end chip model is an IBIS AMI model; and inputting a random code signal to the input end of the channel simulation link, and reading a signal outputted from an output end of the back-end chip and forming an eye pattern.

Abstract: Provided is a circuit structure for suppressing surge current, which includes a surge current suppression judgment circuit, a switching control circuit and a self-boosting regulating circuit. An output end of the surge current suppression judgment circuit is connected with the switching control circuit. An output end of the switching control circuit is connected with the self-boosting regulating circuit. The switching control circuit and the self-boosting regulating circuit are both connected with a current input end Vin. An output end of the self-boosting regulating circuit is connected with an input end of the surge current suppression judgment circuit. The output end of the self-boosting regulating circuit is an output end Vout of the whole circuit structure for suppressing surge current.

Abstract: A clock skew correcting method, device and system are provided. The method includes: determining at least two modules; determining a period of a clock signal and calculating a delay parameter of each of the at least two modules, in a case where a clock generator transmits the clock signal to each of the at least two modules; determining one of the at least two modules as a slave module and the other of the at least two modules as at least one main module; correcting a clock phase for each of the at least one main module based on the delay parameter of the slave module; and performing, for each of the at least one main module, the following step of generating a corrected clock for the main module based on the period and the corrected clock phase for the main module.

Abstract: A power supply system for reducing voltage fluctuation of a rack GPU, which includes: a PSU power supply module, two power supply copper plates including a first power supply copper plate and a second power supply copper plate, two transfer copper plates including a first transfer copper plate and a second transfer copper plate, and two crown clips including a first crown clip and a second crown clip. The PSU power supply module is connected to the first power supply copper plate, the first power supply copper plate is connected to a BUS BAR through the first transfer copper plate and the first crown clip sequentially, the BUS BAR is connected to the second power supply copper plate through the second crown clip and the second transfer copper plate sequentially, and the second power supply copper plate is connected to a GPU module mainboard.

Abstract: A tool-free hard disk mounting and dismounting device is provided according to the present application. The tool-free hard disk mounting and dismounting device includes a fixing support, a spring strip and a handle, wherein the fixing support includes a base plate, a first vertical plate and a second vertical plate, the first vertical plate and the second vertical plate are fixed to two sides of the base plate respectively, and fixing convex portions are provided at two sides of the first vertical plate respectively. The spring strip is fixed to the second vertical plate and located at an outer side of the second vertical plate, a bent portion is provided at each of two ends of the spring strip, a fixing column is provided at each of the bent portions, and a spring strip oblique boss is provided at each of two sides of the spring strip.

Abstract: A method for protecting operation of a server backboard is provided. The method includes: establishing an adaptive setting mechanism for an overcurrent protection point of the server backboard, where a backboard operation overcurrent protection unit is established on a server mainboard and is configured to acquire load information of a current backboard and adjust, based on the load information, an overcurrent protection point of a power supply path provided by the mainboard to the backboard; establishing an automatic current limiting mechanism applied in a case where the backboard is in an overcurrent state; and establishing a server backboard abnormality control unit.

Abstract: The present invention relates to the field of servers, and disclosed thereby is a peripheral component interconnect express (PCIE) structure capable of tool-free disassembly/assembly, including: a node base and a PCIE support, a board card being mounted on the node base, and the board card being provided thereon with a PCIE insertion slot; a Riser card is mounted on the PCIE support, and a PCIE card is mounted within the PCIE slot by means of the Riser card; the PCIE support is detachably mounted on the node base, and the node base on which the PCIE support is mounted may be steadily placed into a machine case. The PCIE structure provided by the present invention may simultaneously lock two adjacent PCIE supports within a node, and no tools are required for the entire assembly and disassembly process.

Abstract: A method and an apparatus for performing a test for a CPU, and an electronic device. A decay command in a SETWP test and a command-executing duration corresponding to each command subsequent to the decay command can be automatically deployed. Thereby, the SETWP test is correctly performed for the CPU to obtain a test result. It is not necessary to rely on manual adjustment on a parameter of a delay corresponding to each command.

Abstract: A buffer bracket for multi layers of expansion cards is provided, which includes: an elastic base, a first supporting plate and a plurality of second supporting plates which are sequentially arranged from bottom to top, wherein the first supporting plate is fixedly connected to the elastic base, the first supporting plate is slidably connected to the adjacent second supporting plate, and the adjacent second supporting plates are slidably connected.

Abstract: A height-adjustable fan fixing structure and a height adjustment method are provided. The height-adjustable fan fixing structure includes a fan box rear cover and a fan box front cover, the fan box rear cover and the fan box front cover cooperating to fix a fan; and further includes a height adjustment block, the height adjustment block being adjustably mounted on a whole piece formed by connection of the fan box rear cover and the fan box front cover, the lower end of the two side surfaces of the height adjustment block being provided with trunkings, each of the trunkings being provided with a rotatable wire screw, positions, corresponding to the two ends of each wire screw, on the fan box rear cover and the fan box front cover being provided with clamping holes, the two ends of the wire screw being inserted into the clamping holes.

Abstract: A method, an apparatus, and a device for transmitting a file based on a BMC, and a medium are provided. The method includes: sending, by using a first BMC, a preset command to a second BMC, before the first BMC transmits a data file to the second BMC; controlling the second BMC to stop an IPMI process running based on an I2C bus in response to the preset command; and controlling the first BMC to transmit the data file to the second BMC by using a communication function of the I2C bus. With the method, when the data file is transmitted between the BMCs, the IPMI process running on the BMC receiving the data file is stopped, such that the data file is not intercepted and verified by the command processing function of the IPMI process, and the IPMI process is prevented from being blocked and crashing.

Abstract: A hot plugging module power supply device, method and system are provided. When a hot plugging module is connected to a system in a hot plugging manner, a control unit transmits a first control signal to a signal processing unit. The signal processing unit forms a switch-on signal and transmits the switch-on signal to a switch unit, to gradually switch on the switch unit, to provide power to the hot plugging module. During the hot plugging module is supplied with power, when an overcurrent fault occurs in the hot plugging module, the control unit transmits a second control signal to the signal processing unit, and the signal processing unit forms a switch-off signal and transmits the switch-off signal to the switch unit, to immediately switch off the switch unit, to stop supplying power to the hot plugging module.