Abstract: A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the cer

Abstract: A composite electronic structure comprising at least one feature layer and at least one adjacent via layer, said layers extending in an X-Y plane and having height z, wherein the structure comprises at least one capacitor coupled in series or parallel to at least one inductor to provide at least one filter; the at least one capacitor being sandwiched between the at least one feature layer and at least one via in said at least adjacent via layer, such that the at least one via stands on the at least one capacitor, and the at least one of the first feature layer and the adjacent via layer includes at least one inductor extending in the XY plane.

Abstract: An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.

Abstract: A structure consisting of at least one die embedded in a polymer matrix and surrounded by the matrix, and further consisting of at least one through via through the polymer matrix around perimeter of the die, wherein typically the at least one via has both ends exposed and where the die is surrounded by a frame of a first polymer matrix and the at least one through via passes through the frame; the die is positioned with terminals on a lower surface such that the lower surface of the chip is coplanar with a lower surface of the frame, the frame is thicker than the chip, and metal is directly attached to and covers at least part of the upper surface of the chip.

Abstract: A structure consisting of at least one die embedded in a polymer matrix and surrounded by the matrix, and further consisting of at least one through via through the polymer matrix around perimeter of the die, wherein typically the at least one via has both ends exposed and where the die is surrounded by a frame of a first polymer matrix and the at least one through via passes through the frame; the die is positioned with terminals on a lower surface such that the lower surface of the chip is coplanar with a lower surface of the frame, the frame is thicker than the chip, and metal is directly attached to and covers at least part of the upper surface of the chip.

Abstract: An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.

Abstract: An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.

Abstract: A multilayer composite electronic structure comprising feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite structure further comprising at least one outer layer of terminations comprising at least one copper post that is only partially embedded in an outer layer of dielectric such that part of the at least one copper post protrudes beyond surface of the outer layer of dielectric.

Abstract: An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.

Abstract: A multilayer electronic support structure including at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one constructional element through the dielectric material spanning between said pair of adjacent feature layers in a Z direction perpendicular to the X-Y plane; wherein said at least one constructional element is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane and wherein the at least one constructional element is fully encapsulated within the dielectric material and is electrically isolated from its surrounding.

Abstract: An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.

Abstract: An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and a method of fabrication, the chip sockets are characterized by being rectangular with smooth walls that meet at corners that have radii of curvature of less than 100 microns thereby facilitating a close fit of each socket to the intended chip size, enabling compact chip packaging and miniaturization.

Abstract: An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.

Abstract: An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesive layer, a layer of pillars extending from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material.

Abstract: A multilayer electronic support structure comprising at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one one non-cylindrical via post that couples said pair of adjacent feature layers through the dielectric material in a Z direction perpendicular to the X-Y plane; wherein said at least one non-cylindrical via post is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane.

Abstract: An acoustic resonator comprising a substantially horizontal membrane of piezoelectric material with upper and lower metal electrodes on its upper and lower faces, said membrane being attached around its perimeter to the inner side walls of a rectangular interconnect frame by an attaching polymer, the side walls of the package frame being substantially perpendicular to the membrane and comprising conducting vias within a dielectric matrix, the conducting vias running substantially vertically within the side walls, the metal electrodes being conductively coupled to the metal vias by a feature layer over the upper surface of the membrane and top and bottom lids coupled to top and bottom ends of the interconnect frame to seal the acoustic resonator from its surroundings.

Abstract: An acoustic resonator comprising a substantially horizontal membrane of piezoelectric material with upper and lower metal electrodes on its upper and lower faces, said membrane being attached around its perimeter to the inner side walls of a rectangular interconnect frame by an attaching polymer, the side walls of the package frame being substantially perpendicular to the membrane and comprising conducting vias within a dielectric matrix, the conducting vias running substantially vertically within the side walls, the metal electrodes being conductively coupled to the metal vias by a feature layer over the upper surface of the membrane and top and bottom lids coupled to top and bottom ends of the interconnect frame to seal the acoustic resonator from its surroundings.

Abstract: An acoustic resonator comprising a substantially horizontal membrane of piezoelectric material with upper and lower metal electrodes on its upper and lower faces, said membrane being attached around its perimeter to the inner side walls of a rectangular interconnect frame by an attaching polymer, the side walls of the package frame being substantially perpendicular to the membrane and comprising conducting vias within a dielectric matrix, the conducting vias running substantially vertically within the side walls, the metal electrodes being conductively coupled to the metal vias by a feature layer over the upper surface of the membrane and top and bottom lids coupled to top and bottom ends of the interconnect frame to seal the acoustic resonator from its surroundings.

Abstract: An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and a method of fabrication, the chip sockets are characterized by being rectangular with smooth walls that meet at corners that have radii of curvature of less than 100 microns thereby facilitating a close fit of each socket to the intended chip size, enabling compact chip packaging and miniaturization.

Abstract: A substrate comprising a capacitor comprising metal electrodes and a ceramic or metal oxide dielectric layer, the capacitor being embedded in a polymer based encapsulating material and connectable to a circuit via a via post standing on said capacitor.