Abstract: In one set of embodiments, a power management system comprises two or more devices, such as POL devices, configured to transmit and receive data over a shared bus, such as an I2C bus, according to the bus protocol of the shared bus. Each device may be configured with at least one respective address register, which may be programmed with an address uniquely identifying the device, and a mask register that may be configured to mask select bits of the respective address register, thereby enabling the device to identify device groups. In one embodiment, one of the devices identifying itself as a master device may distribute information to any of the other devices by transmitting the information, which may include commands and/or data, to itself, in effect targeting the address programmed into its own address register.

Abstract: Rather than operating in asynchronous mode during turn-on ramps, a switching power regulator system may be configured to synthesize a digital waveform, which may protect against a pre-bias condition and maintain the desired ramp-up time and rate. The desired turn-on ramp may be generated digitally by counter logic, beginning with an initial value and incrementing at a programmed rate until a digital value equivalent to the desired output voltage is reached. When a pre-bias condition is not present, the output of the digital ramp generator may control a digital-to-analog converter (DAC), which may be configured to generate the reference voltage for the power regulator. To correct for a pre-bias condition, the pre-bias output of the power regulator may be measured prior to turn-on, using an analog-to-digital converter. The digital pre-bias value may be used to control the DAC until the value of the digital waveform generated by the ramp generator reaches the pre-bias value.

Abstract: Embodiments of a system and method to control the overlap times—and deadtime delays—in power converters may support both overlapping and non-overlapping gate control signals, which may provide improved efficiency optimization across a wider range of applications. Various embodiments may be configured to provide careful partitioning between hardware implementation and software control, in order to better accommodate microprocessor-based power converters. Software algorithms may be used to avoid restrictions such as high gate impedance and changing load effects, and protection against errant operation may be provided using an overlap watchdog circuit. Various control circuits may be operated according to one or more algorithms configured to optimize both the HS-to-LS and LS-to-HS deadtime delays for obtaining minimum possible PWM duty cycle values to achieve improved power efficiency.

Abstract: A distributed power management system may include a digital communication bus and a plurality of POL (point-of-load) regulators coupled to the communication bus and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current. Each POL regulator may have a respective phase in the current sharing configuration, and each POL regulator may transmit and receive information over the bus according to a bus communication protocol corresponding to the bus. Each POL regulator may autonomously add and drop its phase as required by the system, by sequentially manipulating a pulse width of a couple of gate signals configured to respectively control a high-side field effect transistor (FET) and low-side FET in the POL regulator's output stage.

Abstract: The operation of a voltage regulator (or point-of-load regulator) may be optimized, by performing diode emulation using the low-side output transistor (LS FET). The voltage regulator may be monitored for a specified trigger event, which may include an averaged value of the load current dropping below a threshold value, and upon recognizing the trigger event, one or more of a number of possible diode emulation algorithms may be enabled. In one algorithm, the duty-cycle of the LS FET control signal may be set to a specified value, then adjusted until the duty-cycle of the high-side output transistor (HS FET) control signal settles and steady state is reached. The duty-cycle of the LS FET control signal may then be adjusted, and the duty-cycle of the HS FET control signal monitored, until the monitoring indicates that the duty-cycle of the HS FET control signal has reached a minimum value, thereby optimizing operation of the voltage regulator with respect to power loss.

Abstract: Complex filters may be used to achieve compensation of a plant, corresponding for example to a power regulator or point-of-load (POL) regulator. Digital filter coefficients may be mapped to analogous poles and zeros, or they may be mapped to values of the quality factor (Q) of the output, frequency, and gain. The plant may be observed and characterized using a network analyzer to generate the Bode plot (or Nyquist plot) for the plant. The digital filter coefficients may be mapped to features that may be identified on the Bode plot (or Nyquist plot) to easily correlate characteristics of the digital filter or digital compensator to the plant characteristics. The mapped features may be adjusted, for example by a user, either manually or by executing one or more optimization algorithms, to achieve the desired results relative to the Bode plot (or Nyquist plot).

Abstract: Transient processing mechanisms for power converters. Error generation circuitry in a power converter may generate an error signal based on the difference between a power converter output voltage and a reference voltage. Transient detection circuitry may detect whether the error signal exceeds at least a first threshold. If the first threshold is exceeded, timing control logic may generate a low band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the first threshold. If the error signal exceeds a second threshold, the timing control logic may generate a high band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the second threshold. The timing control logic may initiate a low band blanking period following the low band correction pulse and high band blanking period following the high band correction pulse.

Abstract: A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an address group, and may be configured via pin strapping to be able to perform a variety of power management functions. Any one of the POL regulators within the address group may become a bus master and transmit information to the shared bus by addressing itself. The other POL regulators in the address group may monitor the shared bus for events, and may respond to the transmitted information according to their address, their configuration, and the transmitted information. The response may include the POL regulators performing one or more power management functions, including adjusting their respective output voltages.

Abstract: A method for optimizing operation of a feedback system may include generating a control signal according to a control parameter, regulating an output of the feedback system via the control signal, and monitoring the control parameter. In response to the monitoring indicating that the present value of the control parameter is outside a specific range of values, a first parameter that impacts an operating characteristic of the feedback system may be adjusted until the present value of the control parameter is within the specific range of values. The specific range of values of the control parameter may correspond to a target level of the operating characteristic of the feedback system with respect to the first parameter.

Abstract: A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an address group, and may be configured via pin strapping to be able to perform a variety of power management functions. Any one of the POL regulators within the address group may become a bus master and transmit information to the shared bus by addressing itself. The other POL regulators in the address group may monitor the shared bus for events, and may respond to the transmitted information according to their address, their configuration, and the transmitted information. The response may include the POL regulators performing one or more power management functions, including adjusting their respective output voltages.

Abstract: Transient processing mechanisms for power converters. Error generation circuitry in a power converter may generate an error signal based on the difference between a power converter output voltage and a reference voltage. Transient detection circuitry may detect whether the error signal exceeds at least a first threshold. If the first threshold is exceeded, timing control logic may generate a low band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the first threshold. If the error signal exceeds a second threshold, the timing control logic may generate a high band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the second threshold. The timing control logic may initiate a low band blanking period following the low band correction pulse and high band blanking period following the high band correction pulse.

Abstract: A new system-level approach to managing the delivery of DC voltage and current. Several system level functions may be enabled without requiring separate ICs to perform those functions. Supervisory functions for a voltage converter may be performed by a central control module or chip that may be coupled to point-of-load voltage converters comprised in digital power management devices (DPMD) through a serial digital bus. The DPMDs may also use the high-speed serial digital bus to provide real-time feedback information to the central control module or chip. Single DPMDs may be combined together in a current sharing configuration in a “plug-and-play” fashion, where the control logic in each DPMD is capable of automatically establishing control loops required a multi-phase supply. Feedback necessary for establishing control may be transmitted across the digital bus coupling the devices.

Abstract: Rather than operating in asynchronous mode during turn-on ramps, a switching power regulator system may be configured to synthesize a digital waveform, which may protect against a pre-bias condition and maintain the desired ramp-up time and rate. The desired turn-on ramp may be generated digitally by counter logic, beginning with an initial value and incrementing at a programmed rate until a digital value equivalent to the desired output voltage is reached. When a pre-bias condition is not present, the output of the digital ramp generator may control a digital-to-analog converter (DAC), which may be configured to generate the reference voltage for the power regulator. To correct for a pre-bias condition, the pre-bias output of the power regulator may be measured prior to turn-on, using an analog-to-digital converter. The digital pre-bias value may be used to control the DAC until the value of the digital waveform generated by the ramp generator reaches the pre-bias value.

Abstract: A power management system may be configured to allow digital information relating to the power management functions of sequencing and fault spreading to be passed between POL regulators using a standard multi-master multi-slave interface such as I2C bus interface or SMBus interface. POL regulators may be configured via pin strapping, and coupled to a serial data bus where they may monitor bus transactions initiated by other similar POL regulators. Each POL regulator may respond to the bus transactions initiated by other POL regulators according to its configuration, and may perform a variety of tasks associated with sequencing and fault spreading in addition to regulating its own voltage output. When configured with a standard multi-master/multi-slave interface such as an I2C bus interface or SMBus interface, the POL regulators may report information to multiple other POL regulators while maintaining compatibility with non-POL devices also connected to the bus.

Abstract: The control precision of one or more parameters of an integrated circuit (IC), for example the output voltage of a voltage regulator comprised in the IC, may be improved even when using inaccurate components external to the IC. Control of the output voltage, or any parameter, using components external to the IC may include coupling a resistor to the IC and measuring the actual resistance value of the resistor, and based on the measured value, selecting a nominal resistance value from a set of resistance values previously specified by the user. The output voltage, or parameter, may be generated according to the nominal resistance value instead of the actual resistance value, thereby reducing the error that may be incurred due the actual resistance value of the resistor not matching the expected nominal value of the resistor.

Abstract: In one set of embodiments, a power management system comprises two or more devices, such as POL devices, configured to transmit and receive data over a shared bus, such as an I2C bus, according to the bus protocol of the shared bus. Each device may be configured with at least one respective address register, which may be programmed with an address uniquely identifying the device, and a mask register that may be configured to mask select bits of the respective address register, thereby enabling the device to identify device groups. In one embodiment, one of the devices identifying itself as a master device may distribute information to any of the other devices by transmitting the information, which may include commands and/or data, to itself, in effect targeting the address programmed into its own address register.

Abstract: A simple digital-to-analog converter (DAC) may be used to monitor a load current. The DAC may be configured to generate a voltage corresponding to an estimate of an average value of the load current. A comparator may be used to compare that voltage with a sense voltage corresponding to the actual load current. The estimate may then be adjusted based on a sample of the comparator output, allowing the estimate to track the load current over time, thus providing an average measurement capability without using a fast analog-to-digital converter. The DAC may additionally be configured to generate respective voltages corresponding to specified over-current (OC) and under-current (UC) values. The comparator may then be used to compare these respective voltages with the sense voltage to respectively detect OC and UC faults. Noise immunity may be increased by integrating a number of comparator samples instead of a single comparator sample before adjusting the estimate.

Abstract: Adaptive thresholding technique for power supplies during margining events. A power supply may include a fault detection mechanism for monitoring an output voltage of the power supply to determine whether the output voltage is greater than a first over-voltage threshold or less than a first under-voltage threshold. If a margining event changes the power supply output voltage, the fault detection mechanism may dynamically change a first over-voltage threshold and a first under-voltage threshold based on the margining event to a second over-voltage threshold and a second under-voltage threshold. Then, during the margining event, the fault detection mechanism may monitor the output voltage of the power supply to determine whether the output voltage is greater than a second over-voltage threshold or less than a second under-voltage threshold. The fault detection mechanism may dynamically change a fault threshold in proportion to the change in the power supply output voltage.

Abstract: Transient processing mechanisms for power converters. Error generation circuitry in a power converter may generate an error signal based on the difference between a power converter output voltage and a reference voltage. Transient detection circuitry may detect whether the error signal exceeds at least a first threshold. If the first threshold is exceeded, timing control logic may generate a low band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the first threshold. If the error signal exceeds a second threshold, the timing control logic may generate a high band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the second threshold. The timing control logic may initiate a low band blanking period following the low band correction pulse and high band blanking period following the high band correction pulse.

Abstract: A new system-level approach to managing the delivery of DC voltage and current. Several system level functions may be enabled without requiring separate ICs to perform those functions. Supervisory functions for a voltage converter may be performed by a central control module or chip that may be coupled to point-of-load voltage converters comprised in digital power management devices (DPMD) through a serial digital bus. The DPMDs may also use the high-speed serial digital bus to provide real-time feedback information to the central control module or chip. Single DPMDs may be combined together in a current sharing configuration in a “plug-and-play” fashion, where the control logic in each DPMD is capable of automatically establishing control loops required a multi-phase supply. Feedback necessary for establishing control may be transmitted across the digital bus coupling the devices.