Abstract: A sample and hold circuit uses an auto-zero feedback technique to cancel the DC level of the input signal and reference this signal to a new baseline. The circuit is based on an op-amp with two separate feedback loops. The first feedback loop is connected to the same op-amp input as the incoming signal and contains a capacitor to store charge from this signal during sample mode and set the output voltage during hold mode. The second feedback loop uses an auto-zero feedback technique and contains an integrator having a predetermined reference voltage, thereby allowing the DC level of the input signal to removed without the need for capacitors in the gain path of the circuit. This allows the sample and hold circuit to extract an embedded time varying signal from the input voltage. It can be configured for a high gain, high pass function, without the need for large electrolytic capacitors in the gain path, removing the problems associated with such capacitors.