Abstract: A processor having a virtually addressable primary operand register file (PORF) is further provided with an auxiliary operand register file (AORF) to facilitate non-disruptive adjunct Execution. Preferably, the processor is further provided with basic and extended interrupt/exception (I/E) microcode as well as an AORF stack for recursively making available the AORF to the I/E service routines (ISR/ESR), utilizing the AORF stack, for nested servicing of I/E's. In some embodiments, the processor is further provided with micro-trap microcode, a first writable control store facility (WCSF), first auxiliary execution units (AEU) and multiple micro-trap service routines of a first and a second type comprising a number of uniterruptable series' of micro operations for performing complex tasks, leveraging the AORF and optionally the first AEU's.

Abstract: A processor is provided with a number of control registers logically organized in a hierarchical manner. At the highest level is a set of control registers for controlling the overall system. At the second highest level are multiple sets of control registers for controlling concurrent execution of processes in multiple contexts. At the third highest level are multiple sets of control registers for controlling concurrent execution of multiple process threads for each of the concurrently executing contexts. Besides modifications resulting from the normal course of instruction execution, the control registers are directly accessible and modifiable using instructions of the standard instruction set. Each context/thread is assigned a variable privilege level for accessing and modifying control registers at the various levels. The instruction fetch unit is enhanced to dispatch instructions with appended context and tag identifications.