Abstract: An arbitrary waveform generator includes at least one analog output, a digital-to-analog converter connected to the analog output and a waveform source connected to the digital analog converter. The waveform source includes a waveform memory, a signal player and a signal processor. The waveform generator is controlled by a sequencer having an instruction memory for instructions and an instruction interpreter adapted to sequentially execute the instructions. A command table unit, in addition to the sequencer, is connected to the waveform source and includes a command table memory holding a plurality of commands. The commands include a waveform identifier for a waveform to be played and a parameter identifier describing how to modify the waveform in the signal processor. The sequencer can trigger the command table unit to execute a command therein, thereby playing the waveform with the parameter as identified by the command.

Abstract: A system for controlling a quantum processor comprises a controller device having a plurality of input channels and output channels connected to qubit readout instruments and qubit control instruments . The controller device forms a register bank for receiving the data from the input channels , a feedback block for processing the data from the register bank , and an output interface for sending the results of the feedback block to the control instruments . For each input channel , the controller device comprises a mask generator with its own address decoder for processing the update messages on the input channels in parallel. Each update message comprises address data , data values for several registers and validity bits indicating if the data values are valid.

Abstract: A system for controlling a quantum processor includes a system controller having a plurality of input channels and output channels connected to qubit readout instruments and qubit control instruments. The system controller is implemented at least in part as an FPGA. It forms a register bank for receiving the data from the input channels, a feedback block for processing the data from the register bank, and an output interface for sending the results of the feedback block to the control instruments. The feedback block can be programmed by an FPGA configuration device. The FPGA configuration device is able to process various types of feedback block definitions, which e.g. describe lookup tables, minimizers, Boolean operations, etc. A configuration device includes a system compiler agnostic of the specific implementation of the feedback block for controlling the experiments and the operation of the instruments.

Abstract: A device for dynamic signal generation and analysis, which combines an arbitrary waveform generator AWG (3) with a digital signal analysis unit DSAU (23). The two units are interfaced by means of a synchronization unit SU (30), which enables a flexible scheme for controlling how the playback of the waveforms is started as well as synchronizing the recording of the results of the digital signal analysis unit synchronously to specific generated waveforms. The various units of the device are synchronous circuits clocked by a common system clock signal. At least one common numerically controlled oscillator NCO (40) is provided for the arbitrary waveform generator AWG (3) and the digital signal analysis unit DSAU (23).

Abstract: The presented device is the combination of a lock-in amplifier unit (1) and a phase-synchronous processing unit (2). This combination leads to a multitude of valuable signal analysis and conditioning possibilities. Amongst others, these possibilities include (i) extraction of time-domain properties of the input signal, (ii) extraction of statistical properties of the input signal, (iii) extraction of frequency-domain properties of the input signal, and (iv) preconditioning of the lock-in input signal.

Abstract: An apparatus for demodulating an input signal that includes a frequency detector for tracking a frequency of the input signal, an oscillator and a mixer is disclosed. The input signal and an output signal of the oscillator can constitute the incoming signals for the mixer and the output signal of the mixer can constitute the demodulated input signal, wherein an arithmetic unit is arranged downstream of the frequency detector and upstream of the oscillator, wherein the tracked frequency of the input signal and a predefined second frequency constitute the incoming signals of the arithmetic unit and the arithmetic unit is designed such that it computes a control signal for the oscillator from the tracked frequency of the input signal and the predefined second frequency with the output signal of the oscillator depending on the control signal.