Abstract: The present invention provides for a programming portion of an FPGA cell of an integrated circuit and a process of manufacturing the programming portion. The programming portion has an EPROM transistor and a separated select transistor with the gate of the select transistor connected to the control gate of the EPROM transistor. Both transistors share a common N+ source/drain region, which is self-aligned with the gates of both transistors. With the select transistor separated from the EPROM transistor and the self-aligned common N+ region, the threshold voltage V.sub.T of the select transistor can be set precisely. This allows good control over the programming voltage for the control gate of the EPROM transistor and the time to program the floating gate of the EPROM transistor.

Abstract: An array of programmable interconnect cells, each cell having a floating gate as the gate of an MOS switch transistor which programmably connect or disconnects nodes, is used in an FPGA. The floating gate of each cell, which is capacitively coupled to a control gate, is programmed by Fowler-Nordheim tunneling through an tunneling oxide above a programming/erase line in the integrated circuit substrate. Contiguous and parallel to the programming/erase line is at least one tunneling control line which forms a PN junction in close proximity to the programming/erase line region under the tunneling oxide. Under a reverse bias, a deep charge depletion region is formed in the programming/erase line region to block tunneling. In this manner, a selected cell can be programmed/erased, while the non-selected cells are not.

Abstract: The use of daughterboards connecting to a motherboard in an emulation system allows for the upgrading of the emulation field programmable gate arrays in the system, and for the use of different types of field programmable gate arrays. These changes can be made without changing the motherboard. The motherboard has sockets which have pin locations which are allocated to interconnect structures and to an emulation bus. The chips on the cards can contain different emulation field programmable gate arrays, or could contain core chips, which can be directly connected to the motherboard through the daughterboards. The daughterboards connect the emulation FPGAs and the core chips to the correct pin locations of the sockets. Controller chips on the cards allow for different types of field programmable gate arrays to be used and simplify the configuration loading and debugging of the system. Additionally, the present system includes a system using a reconfigurable interface in a controller chip.

Abstract: A field programmable device includes two separate and electrically isolated arrays of rows and columns of conductors sharing the same area of an integrated circuit substrate, one array interconnecting memory cells to form a random access memory ("RAM"). The other array forms a full or partial cross-point switching network that is controlled by information stored in memory cells, and/or connects to an operating electronic circuit that is configurable and operable in accordance with information stored in memory cells. In addition, the memory array is easily used to access desired nodes of the circuit array in order to be able to easily observe internal signals during operation. A preferred memory structure is a dynamic random access memory ("DRAM") because of a high density and low cost of existing DRAM fabrication techniques, even though periodic reading and refreshing of the states of the memory cells is required.

Abstract: The present invention provides for an FPGA integrated circuit having an array of logic cells and interconnect lines interconnected by programmable switches, each formed from a nonvolatile memory cell. The logic cell is designed to provide logic or memory functions according to the setting of programmable switches within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between the wiring segments.

Abstract: A novel method of connecting and operating an NVM transistor in the switching circuit is provided. A full voltage signal can be switched across an NVM transistor. The device is turned on prior to the signal switching and the electrical characteristics of the NVM device relative to the associated circuitry is carefully regulated to prevent the source-drain voltage from rising above a preselected maximum voltage (e.g. 1 v). Two embodiments of the present invention are described. In the first embodiment, the relative impedances of the NVM transistor and its driving circuit are controlled. The driver circuit and the NVM transistor switch act as a resistor divider circuit with a percentage of the full switching voltage appearing across the NVM transistor and the driver circuit according to their relative impedances. The second embodiment is applicable when the NVM transistor switch drives a capacitive load. The rise time of the signal to be switched is controlled.

Abstract: A system for concurrent evaluation of the effect of multiple faults in a logic design being evaluated is particularly useful in the design of very large scale integrated circuits for developing a compact input test set which will permit locating a predetermined percentage of all theoretically possible fault conditions in the manufactured chips. The system includes logic evaluation hardware for simulating a given logic design and evaluating the complete operation thereof prior to committing the design to chip fabrication. In addition, and concurrently with the logic design evaluation, the system includes means for storing large number of predetermined fault conditions for each gate in the design, and for evaluating the "fault operation" for each fault condition for each gate, and comparing the corresponding results against the "good machine" operation, and storing the fault operation if different from the good operation.