Abstract: An interposer is provided that suppresses heat conduction more effectively between two heat sources when the interposer is placed between the heat sources. An interposer 24 comprises a body having a cavity 23 maintained in vacuum; insulating layers 22a and 22b formed respectively on upper and lower walls 20a and 20b of the body; and heat reflecting layers 21a and 21b formed respectively on the insulating layers 22a and 22b. The interposer 24 thermally insulates semiconductor devices 11a and 21a mounted respectively on upper and lower sides of the interposer 24.

Abstract: A method of forming a low-resistance, high-reliability through/embedded electrode is provided, where the electrode can be arranged in a higher density according to the miniaturization of the semiconductor manufacturing technology. This method includes the step of filling an opening 51 of a substrate 50 with a paste 56 of a first conductive material and drying the paste 56; the step of solid-phase sintering the paste 56 filled in the opening 51, generating a first porous conductor 57; the step of applying a paste of a second conductive material so as to cover the first conductor 57; and the step of melting the paste of the second conductive material by heat treatment, impregnating the second conductive material into the first conductor 57.

Abstract: In the conventional high-speed, large-current semiconductor chip, all the electric connecting terminals were placed on one surface of the chip. For this reason, to supply stable supply currents or reduce noises mixed into the signal system from the power supply, many terminals were assigned to supply current inflow terminals and supply current outflow terminals. As a result, there is a problem that the terminal number of a semiconductor device is increased and the mounting area thereof is increased. The electrical connecting terminals for power supply system and those for signal system are separately placed on both sides of a semiconductor chip. By the configuration to enlarging the permissible current value of a path through which a large current flows, stabilization of feeding supply currents, reduction of noises mixed into signal systems, reduction of mounting areas due to pin count reduction, and increase of heat dissipation effects can be realized even with a decreased pin count.

Abstract: A three-dimensional semiconductor integrated circuit device is provided. A first semiconductor chip includes a solid-state circuit and is smaller than a base, and is stacked on the base. The first chip is buried by a first filling material having approximately the same contour as the base. Buried electrodes that penetrate through the first chip along its thickness direction are formed in the first chip. A second semiconductor chip includes a solid-state circuit and is smaller than the base, and is stacked on the first chip. The second chip is buried by a second filling material having approximately the same contour as the base. Buried electrodes that penetrate through the second chip along its thickness direction are formed in the second chip. The first and second filling materials have processibilities required for forming the buried electrodes and thermal expansion coefficients equivalent to those of the first and second chips, respectively.

Abstract: A method of forming a low-resistance, high-reliability through/embedded electrode is provided, where the electrode can be arranged in a higher density according to the miniaturization of the semiconductor manufacturing technology. This method includes the step of filling an opening 51 of a substrate 50 with a paste 56 of a first conductive material and drying the paste 56; the step of solid-phase sintering the paste 56 filled in the opening 51, generating a first porous conductor 57; the step of applying a paste of a second conductive material so as to cover the first conductor 57; and the step of melting the paste of the second conductive material by heat treatment, impregnating the second conductive material into the first conductor 57.

Abstract: To provide a mounting structure of a semiconductor device/electronic component that suppresses temperature rise of a semiconductor device and/or an electronic component having large power consumption due to heat generation thereof, resulting in stable operation. The mounting comprises an interposer 10; a semiconductor device 11 mounted on the surface 10a of the interposer 10; and a cover 12 that forms an inner space S along with the interposer 10; wherein the cover 12 is closely adhered and fixed on the surface 10a of the interposer 10 to so as to include the semiconductor device 11. The cover 12 has an inlet 13 for introducing a heat-absorbing fluid L from outside, and an outlet 14 for discharging the fluid L from the inner space S to outside. The inner space S is a closed space excluding the inlet 13 and the outlet 14.

Abstract: An interposer is provided that suppresses heat conduction more effectively between two heat sources when the interposer is placed between the heat sources. An interposer 24 comprises a body having a cavity 23 maintained in vacuum; insulating layers 22a and 22b formed respectively on upper and lower walls 20a and 20b of the body; and heat reflecting layers 21a and 21b formed respectively on the insulating layers 22a and 22b. The interposer 24 thermally insulates semiconductor devices 11a and 21a mounted respectively on upper and lower sides of the interposer 24.

Abstract: [Aim of Invention] Providing the effective semiconductor miniaturization and its higher-dense fine wiring with the through-hole and the buried via electrode structure of the lower resistivity and higher reliability material at the low cost manufacturing method. [Solution] Preparing the sedimentation layer 57 buried at first the dried-sintered-porous metal material of paste 56 in the through-hole 51 having a insulation layer 54 on the board structure 50, fully covered over the porous area top of the sedimentation layer 57 with the second metal paste and then full-filling the second metal into the porous area of the sedimentation layer 57.

Abstract: A semiconductor device including a semiconductor element and a functional member fixed thereto with an adhesive film is provided, where the performance or reliability degradation due to moisture entered by way of the adhesive film itself or the interfaces between the adhesive film and members adjacent thereto can be suppressed with a simple structure. The semiconductor element has an active region for realizing a predetermined function, formed on a surface of the element. The functional member has a predetermined function and is fixed on a surface side of the semiconductor element with the adhesive film. A metal film covers a region including at least all outer side faces of the semiconductor element, all outer side faces of the adhesive film, an interface between the adhesive film and the semiconductor element, and an interface between the adhesive film and the functional member.

Abstract: A three-dimensional semiconductor integrated circuit device is provided. A first semiconductor chip includes a solid-state circuit and is smaller than a base, and is stacked on the base. The first chip is buried by a first filling material having approximately the same contour as the base. Buried electrodes that penetrate through the first chip along its thickness direction are formed in the first chip. A second semiconductor chip includes a solid-state circuit and is smaller than the base, and is stacked on the first chip. The second chip is buried by a second filling material having approximately the same contour as the base. Buried electrodes that penetrate through the second chip along its thickness direction are formed in the second chip. The first and second filling materials have processibilities required for forming the buried electrodes and thermal expansion coefficients equivalent to those of the first and second chips, respectively.

Abstract: A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film.

Abstract: A semiconductor device including a semiconductor element and a functional member fixed thereto with an adhesive film is provided, where the performance or reliability degradation due to moisture entered by way of the adhesive film itself or the interfaces between the adhesive film and members adjacent thereto can be suppressed with a simple structure. The semiconductor element has an active region for realizing a predetermined function, formed on a surface of the element. The functional member has a predetermined function and is fixed on a surface side of the semiconductor element with the adhesive film. A metal film covers a region including at least all outer side faces of the semiconductor element, all outer side faces of the adhesive film, an interface between the adhesive film and the semiconductor element, and an interface between the adhesive film and the functional member.

Abstract: A method of fabricating a semiconductor device having a three-dimensional stacked structure is provided, which realizes easily the electrical interconnection between the stacked semiconductor circuit layers along the stacking direction by using buried interconnections. The trench 13, the inner wall face of which is covered with the insulating film 14, is formed in the surface of the semiconductor substrate 11 of the first semiconductor circuit layer 1a. Then, the inside of the trench 13 is filled with a conductive material, thereby forming the conductive plug 15. Next, the desired semiconductor element is formed on the surface or in the inside of the substrate 11 in such a way as not to overlap with the trench 13, and the multilayer wiring structure 30 is formed over the semiconductor element through the interlayer insulating film 19. Thereafter, the bump electrode 37, which is electrically connected to the plug 15, is formed on the surface of the multilayer wiring structure 30.

Abstract: A three-dimensional stacked structured semiconductor device comprising semiconductor circuit layers stacked on a support substrate, and a method of fabricating the device are provided. After fixing semiconductor chips 37 to a support substrate 31 with bump electrodes, gaps between the chips 37 are filled with an electrically insulative adhesive 38. Then, by polishing the reverses of the chips 37, the chips 37 are thinned to expose buried interconnections in the chips 37, thereby forming a first semiconductor circuit layer L1. Next, after fixing semiconductor chips 43 to the first semiconductor circuit layer L1 with bump electrodes 41 and 42 by way of an insulating layer 39, gaps between the chips 43 are filled with an electrically insulative adhesive 44. Then, by polishing the reverses of the chips 43, the chips 43 are thinned to expose buried interconnections in the chips 43, thereby forming a second semiconductor circuit layer L2.

Abstract: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.

Abstract: A solid-state image sensor has a chip-size package, which can be easily fabricated. The element-formation regions are formed in the semiconductor substrate (21) of the light-receiving element layer (20) corresponding to the pixel regions. The semiconductor light-receiving elements (PD) are formed in the respective element-formation regions and covered with the light-transmissive insulator films (25a), (25b) and (26). The light-introducing layer (40), which includes the light-introducing cavity (42) and the quartz cap (51) for closing the cavity, is formed on the film (26). The microlenses (43) are incorporated into the cavity (42). The electric output signals of the semiconductor light-receiving elements (PD) are taken out to the bottom of the substrate (21) by way of the buried interconnections of the substrate (21) and then, derived to the outside of the image sensor by way of the output layer (10) or the interposer (10A).

Abstract: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.

Abstract: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.