Abstract: An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

Abstract: The present invention provides an apparatus and method for detecting flatness and/or unevenness of a surface of an overcoat layer on a colored pixel layer of a color filter with a high degree of accuracy. The apparatus includes: a light source 34, placed almost directly above the surface of a plate 30, for emitting an emission-line spectrum corresponding to at least one color of coloring particles in a color filter 32; a photo-receiver 36, placed obliquely upward with respect to the surface of the plate 30 and having a spectral sensitivity corresponding to the emission-line spectrum of the light source, for receiving reflected light from the color filter 32 on the plate 30 during inspection; and a detection means 42 for creating a brightness distribution for a color using a color signal output from the photo-receiver 36 as corresponding to its spectral sensitivity to detect the flatness (unevenness) of the surface of an overcoat layer 16.

Abstract: A stacked multiple electronic component interconnect structure includes a connector portion having a first and second connector surfaces. A first double sided land grid array having a first surface provided with a first plurality of connector units and a second surface provided with a second plurality of connector units, is positioned on the first connector surface. A second double sided land grid array having a first surface provided with a first plurality of connector units and a second surface provided with a second plurality of connector units is positioned on the second connector surface. A first electronic component is mounted to the second surface of the first land grid array and a second electronic component is mounted to the second surface of the second land grid array to form a stacked multiple electronic component interconnect structure that conserves space on an electronic board.

Abstract: A converter program creates a simulated executable portion of code so that the operating system loader believes that a read only file stored on a hard drive of data consists of executable code and thereby memory-maps the read only file into virtual memory from storage. The result is that a large database may be memory-mapped into the processor virtual memory instead of the file having to be opened using standard file application program interface operations.

Abstract: A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by consistent subsets thereof. The method selects the resistance and source values in a Norton or Thevenin circuit used to enforce the IC, and detects when specified ICs are inconsistent while preserving critical or fragile ICs when a two DC-pass approach is used. It further correlates the set of consistent ICs thus obtained with an equivalent circuit and simultaneously provides an input for future use. This allows a user to be notified and given a measure of how bad the inconsistencies are. Detecting inconsistencies is achieved either by measuring the holding current or by measuring the voltage drift if the two DC-pass approach is used.

Abstract: Method and device for verifying the security of a computing platform. In the method for verifying the security of a computing platform a verification machine is first transmitting a verification request via an integrity verification component to the platform. Then the platform is generating by means of a trusted platform module a verification result depending on binaries loaded on the platform, and is transmitting it to the integrity verification component. Afterwards, the integrity verification component is determining with the received verification result the security properties of the platform and transmits them to the verification machine. Finally, the verification machine is determining whether the determined security properties comply with desired security properties.

Abstract: A system for providing a touch interface on a display are described. The system include providing an emitter on a first side of the display and providing a detector on a second side of the display. The emitter provides an electromagnetic signal to the display. The electromagnetic signal has a path from the emitter to the detector through the display in the absence of a user's touch such that the electromagnetic signal is detected by the detector in the absence of the user's touch. The path includes at least one total internal reflection in the display. The emitter and the detector are configured such that the user's touch at any of the at least one total internal reflection alters the path such that a portion of the electromagnetic signal does not reach the detector.

Abstract: A method of synchronizing an audio and visual presentation in a multi-modal browser. A form is transmitted over a network having at least one field requiring user supplied information to a multi-modal browser. Blank fields within the form are filled in by user who provides either verbal or tactile interaction, or a combination of verbal and tactile interaction. The browser moves to the next field requiring user provided input. Finally, the form exits after the user has supplied input for all required fields. The method also provides a synchronized verbal and visual presentation by said browser by having the headings for the fields to be filled out and typing in what the user says.

Abstract: A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap.

Abstract: A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.

Abstract: Provided are techniques for restoring firmware. A first programmable hardware device determines that a second programmable hardware device needs a valid firmware image, retrieves a copy of the valid firmware image from an external memory, and sends the valid firmware image to the second programmable hardware device via a private communication link, wherein the private communication link enables private communication between the first programmable hardware device and the second programmable hardware device. The second programmable hardware device restores existing firmware using the valid firmware image.

Abstract: An apparatus for generating an output signal that is analogous to an first signal from a first signal source that exhibits a first jitter, so that the output signal exhibits less jitter than the first jitter includes at least one second signal source generates a second signal that is analogous to and phase locked with the first signal. The second signal exhibits a second jitter that is uncorrelated with the first jitter. A signal averaging device is responsive to the first signal and the second signal. The signal averaging device averages the first signal and the second signal with respect to at least one parameter and thereby generates the output signal.

Abstract: Systems and methods are provided for maximizing call throughput in a server network by optimizing the balance of stateful to stateless handling or transactions at each server within the network. The identification of transaction messages to be handled statelessly or statefully is made at each proxy server within the network in order to maximize the total throughput at that proxy server within prescribed processor utilization limits. In general, each transaction is handled statefully by at least one server within the network. Reports on the stateful handling of messages and the resource consumption at various proxies are communicated throughout the network to be used in identifying the ratio of messages to be forwarded statefully to messages to be forwarded statelessly at any given proxy.

Abstract: A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

Abstract: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.

Abstract: A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N?) of the netlist. A space state (S?) is created by enumerating the states of N? from which the identified target may be asserted. A constraint space C? is then derived from the state space S?, where C? is the logical complement of S?. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.

Abstract: A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

Abstract: In a telecommunication system adapted to exchange n-bit frames according to a dynamic time division multiplexing access method for a maximum of N accessible channels, the use of a shadow time slot assignment table is eliminated by use of a circuit that includes (a) an n×p memory block to store a time slot assignment table which describes the different time slot assignments by specifying which logical channel each bit position of an n-bit frame belongs to, (b) a register having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto, and (c) a logic circuit connected to the memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, O?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract: A cooperative data stream processing system is provided that utilizes a plurality of independent, autonomous and possibly heterogeneous sites in a cooperative arrangement to process user-defined job requests over dynamic, continuous streams of data. A mechanism is provided for orchestrating the execution of distributed jobs across the plurality of distributed sites. A distributed plan is created that identifies the processing elements that constitute a job that is derived form user-defined inquiries. Within the distributed plan, these processing elements are arranged into subjobs that are mapped to various sites within the system for execution. Therefore, the jobs are then executed across the plurality of distributed sites in accordance with the distributed plan. The distributed plan also includes requirements for monitoring of execution sites and providing for the back-up of the execution sites in the event of a failure on one of those sites.

Abstract: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

Abstract: A system, method and computer program product for performing blind change detection audio segmentation that combines hypothesized boundaries from several segmentation algorithms to achieve the final segmentation of the audio stream. Automatic segmentation of the audio streams according to the system and method of the invention may be used for many applications like speech recognition, speaker recognition, audio data mining, online audio indexing, and information retrieval systems, where the actual boundaries of the audio segments are required.

Abstract: A method, an apparatus, and computer instructions are provided for a secure network install. One aspect of the present invention provides a proxy server within the same subnet of the client for performing a lookup of the boot image file and downloading the boot image file from a boot file server in a secure manner. The client in turn downloads the file from the proxy TFTP server. Another aspect of the present invention modifies the client remote boot code to include a secure boot file download discovery (SBDD) mode. The client starts the SBDD mode by sending a request for a boot image file to a subnet broadcast address and port, which is listened by a proxy TFTP server. The proxy TFTP server receives the client request and downloads the boot image file. The client in turn downloads the boot image file from the proxy TFTP server.

Abstract: A data visualization device comprises a focal attribute calculator for calculating a focal value of each of a plurality of data input items, and for categorizing each of the plurality of data input items as either non-cluster blobs or second blobs. The device further comprises a clustering attribute calculator for clustering data input items categorized as second blobs into one or more cluster blobs, and a visualization shaper for arranging the one or more cluster blobs and the non-cluster blobs, relative to each other in accordance with the focal values of the data input items of respective blobs.

Abstract: A method, grid computing environment, and computer readable medium for managing available resources in a grid computing environment are disclosed. The method includes determining, when a new job is submitted, if a first of the computing clusters has sufficient available resources to run the new job. If the first computing cluster does not have sufficient available resources to run the new job, the method further includes determining if a second of the computing clusters has sufficient available resources to run a first job that is currently running on the first computing cluster. If the second computing cluster has sufficient available resources to run the first job, the first job is migrated to the second computing cluster.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: A system, method and article of manufacture are provided for the automatic recovery from errors encountered during an automated Licensed Internal Code (LIC) update on a storage controller. The present invention functions with a concurrent or nonconcurrent automated LIC update. The automated recovery from many error conditions is transparent to the attached host system and on-site service personnel, resulting in an improvement in the LIC update process.

Abstract: A method is disclosed to detect and repair a broken dataset. The method creates and maintains a backup log and an update log for a dataset. If the method finds a dataset structural error, then the method deletes the corrupted dataset, obtains the most current backup copy of the dataset, obtains all dataset updates made after the most current backup copy of the dataset was saved, and generates a recovered dataset using the most current backup and the dataset updates.

Abstract: An apparatus, system and method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The apparatus includes a detection module to detect an incoming address on the I2C bus, a translation module to translate the incoming address to an outgoing address, and a communication module to communicate data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, the present invention avoids address conflicts between commonly addressed slave devices while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.

Abstract: A cooperative data stream processing system is provided that utilizes a plurality of independent, autonomous and potentially heterogeneous sites in a cooperative arrangement to process user-defined inquiries over dynamic, continuous streams of data. The system derives jobs from the inquiries and these jobs are executed on the various distributed sites by executing applications containing processing elements on these sites. Therefore, components of a given job can be executed simultaneously and in parallel on a plurality of sites within in the system. The sites associated with a given job execution have the need to share data, both primal and derived. A tunnel mechanism is provided that establishes tunnels between pairs of sites within the system. Each tunnel includes either a sink processing element on an originating site and a source processing element on a destination site or a gateway processing element on each site and a network connection between the sink and source processing elements.

Abstract: A method, apparatus, and computer instructions for managing email messages. Outgoing packets are monitored. The outgoing packets are parsed for outgoing email messages. An identification of recipients in packets for outgoing email messages is made. A list of email addresses is updated with email addresses for the identified recipients, wherein the list of email addresses is used to accept incoming email messages. The outgoing packets also are parsed to identify Web traffic containing a user email address. A domain name of the destination is identified for Web traffic containing the user email address. The list of email messages is updated with this domain name. Incoming email messages are screened to see if the domain name is present in the email address of the sender in determining whether to accepted the email messages.

Abstract: An apparatus and method for partitioning programs between a general purpose core and one or more accelerators are provided. With the apparatus and method, a compiler front end is provided for converting a program source code in a corresponding high level programming language into an intermediate code representation. This intermediate code representation is provided to an interprocedural optimizer which determines which core processor or accelerator each portion of the program should execute on and partitions the program into sub-programs based on this set of decisions. The interprocedural optimizer may further add instructions to the partitions to coordinate and synchronize the sub-programs as required. Each sub-program is compiled on an appropriate compiler backend for the instruction set architecture of the particular core processor or accelerator selected to execute the sub-program. The compiled sub-programs and then linked to thereby generate an executable program.

Abstract: A method, system, and program for minimizing complex decisions to allocate additional resources to a job submitted to a grid environment are provided. First, at least one decision to allocate additional resources to at least one previously submitted job is stored in a decision cache, wherein said the least one decision is stored according to at least one characteristic of the at least one previously submitted job. When another job is submitted to the grid environment needs additional resources, the characteristic of the currently submitted job is compared with the characteristics of previous submitted jobs. If there is a match, then the previously made decision associated with the matching characteristic controls allocation of additional resources for the currently submitted job, such that complex decision making for allocation of additional resources is minimized by reusing previously stored decisions to allocate additional resources.

Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract: A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating material. Each end portion of an upper surface of the heating material is connected to a metal terminal. These metal terminals, which are in contact with the end portions of the upper surface of the heating material, can be each connected to an outside component that controls and switches the resistance states of the two programmable vias. The two programmable vias of the inventive structure are each connected to another metal terminal. These metal terminals that are associated with the programmable vias can be also connected to a circuit block that may be present in the structure.

Abstract: Provided are techniques for restoring firmware. A first programmable hardware device determines that a second programmable hardware device needs a valid firmware image, retrieves a copy of the valid firmware image from an external memory, and sends the valid firmware image to the second programmable hardware device via a private communication link, wherein the private communication link enables private communication between the first programmable hardware device and the second programmable hardware device. The second programmable hardware device restores existing firmware using the valid firmware image.

Abstract: A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket.

Abstract: A data processing system employing identify indicators associated with various components of the system. The indicator may be activated whenever a corresponding component requires maintenance, field testing, installation, replacement, and the like. The user may specify global and local conditions under which an activated identify indicator is reset. After the indicator is activated, the system monitors for the satisfaction of one of the conditions. When one of the conditions is satisfied, the system deactivates the indicator automatically. The global conditions apply across logical partitions in a logically partitioned system thereby reducing the occurrence of stale identify indicators on all partitions.

Abstract: A computer program product and database driver for connecting a client to a database server are provided. The computer program product and database driver provide for providing a generic interface, the generic interface being operable to interoperate with one or more non-GSSAPI (Generic Security Services Application Programming Interface) compliant security mechanisms, providing a set of specialized interfaces, the set of specialized interface being operable to interoperate with one or more GSSAPI compliant security mechanisms, and establishing a connection between a client and a database server using the generic interface or the set of specialized interfaces depending on a security mechanism used by the client. The one or more non-GSSAPI compliant security mechanisms and the one or more GSSAPI compliant security mechanisms may be predefined or user-defined.

Abstract: A system maps a multidimensional model to data warehouse schema. The system includes a multidimensional model editor for defining a multidimensional model based on a conceptual model; a mapping reasoner for generating more simple mappings from basic mappings by reasoning on the conceptual model so as to provide mappings for concerning elements in an ontology path in the multidimensional model; a data warehouse schema analyzer for generating a data structure capable of indicating information of the data warehouse schema by making an analysis on the information of the data warehouse schema; and a mapping composition engine for generating result mappings according to mappings for the concerning elements of the ontology path in the multidimensional model and by searching in the data structure paths corresponding to the concerning elements of the ontology path in the multidimensional model. A method and computer program product are also disclosed.

Abstract: A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.

Abstract: A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.

Abstract: An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.

Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Abstract: An invention is disclosed for dynamically changing the predefined execution sequence of steps or tasks in a computerized process while it is being performed by permitting one or more task(s) to be specified as necessary when other task(s) have been completed. Specifically, a product, method and system is provided for using a “workflow engine” software program acting in combination with a “decision-making layer” program interface between the workflow engine and the process model to determine the normal or (“default”) next step in the process and all other possible process steps that can be permissibly completed after execution of the current step or task.

Abstract: System method and program for controlling access to a VLAN via a port of a VLAN switch system. In response to receipt of a message packet at the port, the switch system determines if a MAC address of the packet matches a MAC address for which the port has been programmed to recognize as a MAC address of a device authorized to communicate with the port. The MAC address of the packet does not match a MAC address for which the port has been programmed to recognize as a MAC address of a device authorized to communicate with the port. In response, the switch system blocks the packet if a rate of ill-formed packets and/or packets from an unrecognized MAC address exceeds a threshold pass rate. The threshold pass rate can be adjusted based on the rate of change of receipt of ill-formed packets and/or packets from an unrecognized MAC address.

Abstract: Controlling delivery of broadcast encryption content for a network cluster from a content server outside the cluster that include receiving in the content server from the network device a key management block for the cluster, a unique data token for the cluster, and an encrypted cluster id and calculating a binding key for the cluster in dependence upon the key management block for the cluster, the unique data token for the cluster, and the encrypted cluster id. In typical embodiments, calculating a binding key includes calculating a management key from the key management block for the cluster; calculating a content server device key from the management key and the content server device id; decrypting the encrypted cluster id with the content server device key; and calculating the binding key with the management key, the unique data token for the cluster, and the cluster id.

Abstract: A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.

Abstract: A method of patterning a semiconductor substrate includes creating a first set of patterned features in a first inorganic layer; creating a second set of patterned features in one of the first inorganic layer and a second inorganic layer; and transferring, into an organic underlayer, both the first and second sets of patterned features, wherein the first and second sets of patterned features are combined into a composite set of patterned features that are transferable into the substrate by using the organic underlayer as a mask.

Abstract: A method, computer program product, and a data processing system that facilitates navigation through a directed graph for selection of sub-processes of a modified business process derived from a business process is provided. A bounding box is used for evaluating and selecting sequences of nodes representative of business sub-processes or services. The bounding box has a predefined depth for limiting the scope of the evaluation. The bounding box is shifted during the evaluation as sequences of nodes are selected. Additionally, state data is maintained such that a sense response model may be employed to detect and account for changes to the environment in previously evaluated services.