Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: A voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.

Abstract: A system and method are provided to alert two mobile communications users in the event they come in close proximity to one another. The present system uses a distributed algorithm denoted as the Strips algorithm, in which a pair of moving friends with mobile telecommunications devices makes an agreement about a static buffering region between them. After the agreement is made, the users do not need to follow each other's location until one of them enters the buffering region for the first time. By doing so, they invalidate the agreement. Consequently, they replace a location update message between them, determine if they got within the vicinity of each other, and otherwise make a new agreement on a new buffering region. When one of them enters the buffering region for the first time, a message is sent to both friends alerting them of the proximity of the other.

Abstract: A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation.

Abstract: An apparatus, system, and method are provided for passing data between an XML document and a hierarchical database. The apparatus, system, and method include a hierarchical database, a metadata schema, and a mapping module. The hierarchical database comprises a conventional hierarchical database, such as IMS. The metadata schema is derived from the hierarchical database. The metadata schema includes a first representation representative of the hierarchical structure of the hierarchical database, a second representation representative of the hierarchical structure of XML documents valid for passing into and out of the hierarchical database, one or more database field names, and one or more XML element names that map to the one or more database field names. The mapping module passes data between the XML document and the hierarchical database using the metadata schema.

Abstract: A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, “dummy” instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.

Abstract: Personalized searching including providing in a search portal a personal search term list; receiving from a user a navigation identification message; and inserting index records in a personalized search index. Inserting index records in a personalized search index typically comprises retrieving a document from a navigation location and indexing the navigation location and keywords from the personal search term list that occur in the retrieved document. A navigation identification message may comprise a search keyword and inserting index records in a personalized search index may include indexing the search keyword with the navigation location in the personalized search index. Embodiments typically include creating and transmitting to users, in dependence upon the personalized search index, search criteria, and user identification, responses to search query messages.

Abstract: A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating) layer on the top of the hole layer, and (c) a patterned photoresist layer on top of the BARC layer and having a photoresist hole; etching the BARC layer through the photoresist hole to extend the photoresist hole to the hole layer; performing the chemical shrinking process to shrink the extended photoresist hole; and etching the hole layer through the shrunk, extended photoresist hole so as to form a hole in the hole layer.

Abstract: A novel Active Pixel Sensor (APS) cell structure and method of manufacture. Particularly, an image sensor APS cell having a predoped transfer gate is formed that avoids the variations of Vt as a result of subsequent manufacturing steps. According to the preferred embodiment of the invention, the image sensor APS cell structure includes a doped p-type pinning layer and an n-type doped gate. There is additionally provided a method of forming the image sensor APS cell having a predoped transfer gate and a doped pinning layer. The predoped transfer gate prevents part of the gate from becoming p-type doped.

Abstract: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.

Abstract: A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

Abstract: In a first aspect, a first method is provided for reducing memory errors. The first method includes the steps of (1) detecting at least one error in data output from a first physical memory unit (PMU) of a memory; (2) detecting at least one error in data output from a second PMU of the memory; and (3) setting a bit indicating respective data output from a plurality of PMUs includes errors. Numerous other aspects are provided.

Abstract: A mixed-signal chip having a signal transformer located between analog circuitry and digital circuitry. The signal transformer includes a primary winding electrically coupled to the analog circuitry and a secondary winding electrically coupled to the digital circuitry. The primary and secondary windings are magnetically coupled with one another via a magnetic core. The magnetic coupling between the primary and secondary windings inhibits the coupling of electrical noise between the analog and digital circuitries.

Abstract: A method for providing bounded latency in a real-time data processing system is disclosed. Initially, a batch size is selected. Then, a worst case real time bandwidth (WCRTB) and a bytes-in-batch (BIB) are assigned. Next, a worst case data movement time (WCDMT) is calculated by using the WCRTB and BIB. A processor available cycles per second (PACPS), a processor cycle per sample to execute a function (K), a batch period (P) and a sample period (T) are then assigned. A required function cycles per second (RFCPS) is calculated by using the K and T. Subsequently, a BET is calculated by using the P, RFCPS and PACPS. Finally, BET is maintained to be less than P for ensuring the real-time data processing system to function properly.

Abstract: A method, apparatus, and computer instructions for local program reorganization using branch count per instruction hardware. In a preferred embodiment, a hardware counter is used in the present invention to count the number of times a branch is taken when branch instructions are executed. Branch count statistics generated from the hardware counters are available to a program in order to analyze whether code reorganization is necessary. If reorganization is necessary, the program autonomically reorganizes instructions locally at run time to allow more instructions to be executed prior to taking a branch, so that the number of branches taken is minimized without modifying underlying program code.

Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

Abstract: A topcoat material for applying on top of a photoresist material is disclosed. The topcoat material comprises at least one solvent and a polymer which has a dissolution rate of at least 3000 ?/second in aqueous alkaline developer. The polymer contains a hexafluoroalcohol monomer unit comprising one of the following two structures: wherein n is an integer. The topcoat material may be used in lithography processes, wherein the topcoat material is applied on a photoresist layer. The topcoat material is preferably insoluble in water, and is therefore particularly useful in immersion lithography techniques using water as the imaging medium.

Abstract: A system and method for directing a data processing system to incrementally process a base table and a materialized view, wherein the materialized view is associated with the base table, and both are stored in the system, is disclosed. The method includes setting integrity of the base table having an identifier identifying data newly load appended to the base table, and placing the identifier into a location if the location does not contain any other identifier identifying any other data newly load appended to the base table. In a preferred embodiment, the materialized view is incrementally refreshed using the identifier.

Abstract: A program which is linked or bound by reference (referenced program) into one or more other programs supports multiple valid export signatures, each corresponding to a respective version of the referenced program. When a program is built, it records the current signature of each referenced program it is bound to. When subsequently determining whether to rebuild the program, the previously recorded signature of any referenced program is compared with all currently supported signatures of the referenced program, and only if none of the supported signatures matches does the program need to be re-built to ensure compatibility with the referenced program. Preferably, the referenced program is a program library containing supporting procedures, intended to be used by multiple applications programs which are bound to it.

Abstract: A system and method of squeezing slabs of memory empty are provided. A slab is a block of allocated memory space that is dedicated to holding one type of data. When it is determined that a slab of memory is to be squeezed empty, no object may be allocated from the slab. That is, new data is precluded from being placed in any unused space of the slab. Further, data is also precluded from being placed in any space in the slab that becomes unused anytime thereafter. When the slab becomes empty, the slab is de-allocated.

Abstract: During a parity update of a parity stripe in a disk array, constant values used in finite field arithmetic are algebraically combined in order to reduce the number of buffers and steps needed to update multiple parity values when a change in data occurs. In one implementation, for example, the contents of a buffer that stores the product of a delta value associated with the change in data and a first constant, which is used to update a first parity value, are multiplied by a value representative of the ratio of a second constant, which is used to update a second parity value, and the first constant.

Abstract: The current invention relates to a data mining technology for determining association rules within a multitude of N transactions each transaction comprising up to p different items. According to the invention a sample size n of the multitude of N transactions is determined based on precision requirements. The sample size n is chosen such, that it is at least in the order of magnitude of an estimated sample size n*. Finally association rules are computed based on a sample of the multitude of N transactions with sample size n according to any methodology for mining of association rules using the association rules as estimated association rules of the multitude of N transactions.

Abstract: In response to receiving an initialization operation from an associated processor core that indicates a target memory block to be initialized, a cache memory determines a coherency state of the target memory block. In response to a determination that the target memory block has a data-invalid coherency state with respect to the cache memory, the cache memory issues on a interconnect a corresponding initialization request indicating the target memory block. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value. The target memory block may thus be initialized without the cache memory holding a valid copy of the target memory block.

Abstract: Methods of etching silicon nitride material, and more particularly, etching nitride selective to silicon dioxide or silicide, are disclosed. The methods include exposing a substrate having silicon nitride thereon to a plasma including at least one fluorohydrocarbon and a non-carbon containing fluorine source such as sulfur hexafluoride (SF6). The plasma may also include oxygen (O2) and the fluorohydrocarbons may include at least one of: trifluoromethane (CHF3), difluoromethane (CH2F2), and methyl fluoride (CH3F). In an alternative embodiment, the plasma includes one of hydrogen (H2) and nitrogen trifluoride (NF3) and one of tetrafluoromethane (CF4) and octafluorocyclobutane (C4F8). The methods are preferably carried out using a low bias voltage, e.g. <100 V.

Abstract: A method to update a data structure is disclosed. The method receives a write thread, and sets a data structure indicator to indicate that the data structure is unusable. The method creates (N) thread indicators, and assigns each of said (N) indicators to a different one of said (N) threads. Upon return to the thread dispatcher, the (i)th thread sees the data structure indicator which shows that the data structure is unusable. The method then sets the (i)th thread indicator to indicate that upon subsequent dispatches the (i)th thread will see the data structure indicator that shows that the data structure is unusable. After each of the (N) threads has seen the data structure indicator marking the data structure as unusable, the method sets the data structure indicator to indicate that the data structure is invalid, updates the data structure, and sets the data structure indicator to indicate that the data structure is valid.

Abstract: The invention relates to a method and apparatus for recording and maintaining stored information system object relationship information. Information contained within a stored information system (including system catalogs, referential constraints, triggers, table hierarchies, column references, indexes, stored program packages, system catalogs, stored procedures, stored queries, log/trace files of dynamically executed code, etc.) are searched to identify dependency relationships between objects. This object relationship information is stored and maintained in an information base. Information within the information based may be organized based upon subsets of objects that support a common application, service, or capability.

Abstract: Methods of forming and assemblies having hybrid interconnection grid arrays composed of a homogenous mixture of Pb-free solder joints and Pb-containing solder paste on corresponding sites of a printed board. The aligned Pb-free solder joints and Pb-containing solders are heated to a temperature above a melting point of the Pb-free solder joint for a sufficient time to allow complete melting of both the Pb-free solder joints and Pb-containing solder paste and the homogenous mixing thereof during assembly. These molten materials mix together such that the Pb from the Pb-containing solder disperses throughout substantially the entire Pb-free solder joint for complete homogenization of the molten materials to form the homogenous hybrid interconnect structures of the invention.

Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and ?0.5V for pFETs.

Abstract: A system and method for installing and retaining an input/output connector without tools is presented. A user removes a module from a computer system in order to add or remove a transceiver. The module includes a housing and a front bezel, whereby a bezel latch attaches the front bezel to the housing. The user depresses the bezel latch to remove the front bezel from the housing. As a result, a retention beam is exposed on the housing that secures transceivers to a circuit board. The user unlatches the retention beam, inserts a transceiver onto a mounting area, and latches the retention beam. The retention beam applies pressure to the transceiver, which results in a coupling of the transceiver to a circuit board included in the housing. In turn, the user attaches the front bezel to the housing via the bezel latch and reinserts the module into the computer system.

Abstract: A system for providing document conversion services that uses XML (eXtensible Mark-up Language). A document type definition (DTD) defines tags and attributes for document conversion services, and includes a number of global variable definitions. Each “convertor” tag defines a document conversion filter, using a “filter” tag contained within it. Within each convertor tag, multiple input and output tags describe the capabilities of the convertor, and can be used to define the input document types and output document types for the associated filter. The filter tag can have a “class” attribute or the like, that may be used to provide a fully qualified class name for the filter. A “remote” tag defines whether the conversion for an associated filter is performed on an identified remote server computer system. The global variables are visible to all the convertor entities and may be used to activate logging of activities for various purposes.

Abstract: The present invention provides a multiphase, ultra low k film which exhibits improved elastic modulus and hardness as well as various methods for forming the same. The multiphase, ultra low k dielectric film includes atoms of Si, C, O and H, has a dielectric constant of about 2.4 or less, nanosized pores or voids, an elastic modulus of about 5 or greater and a hardness of about 0.7 or greater. A preferred multiphase, ultra low k dielectric film includes atoms of Si, C, O and H, has a dielectric constant of about 2.2 or less, nanosized pores or voids, an elastic modulus of about 3 or greater and a hardness of about 0.3 or greater. The multiphase, ultra low k film is prepared by plasma enhanced chemical vapor deposition in which one of the following alternatives is utilized: at least one precursor gas comprising siloxane molecules containing at least three Si—O bonds; or at least one precursor gas comprising molecules containing reactive groups that are sensitive to e-beam radiation.

Abstract: A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.

Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.

Abstract: A touch pad for a data processing system includes a first film and an electrically conductive first thin film above the first film, a plurality of electrically non-conductive spacer dots above the first thin film, a second electrically conductive thin film above the plurality of spacer dots, and a second film above the second thin film. The density of spacer dots above the first thin film is non-uniform. In one implementation, the first film is a ceramic, the second film is a flexible polymer, and the first and second thin films are a metal-oxide compound. In one embodiment, the spacer dot density is in a first range over a first portion of the first film and in a second range over a second portion of the first film. The second portion of the first film may define a signature box suitable for receiving a user's signature.

Abstract: A h9eat sink device for conventional memory modules, such as DIMMs, that is configured to be positioned between adjacent memory modules mounted in substantially parallel connectors on a printed circuit board. Each heat sink device includes thermally conductive first and second members configured to thermally couple with electronic components of a conventional memory module. The first and second members may be resiliently biased away from one another so that the resilient bias causes the members to abut respective electronic components when placed between adjacent memory modules. A separate wedge, or a lever-mounted wedge, may be provided for insertion between the members to urge them away from one another and into abutting relationship with electronic components on facing surfaces of the adjacent memory modules. When abutting opposing electronic components, a single heat sink device facilitates heat dissipation from both of the adjacent memory modules.

Abstract: Methods for displaying a set of hierarchical data and a set of non-hierarchical data on an electronic display comprise displaying at least part of the set of hierarchical data in a tree diagram that has a plurality of levels with one or more nodes present at each level, and displaying the set of non-hierarchical data in a plurality of auxiliary nodes that are provided in between levels of the tree diagram. Expansion handles may also be displayed adjacent nodes in the tree diagram. These expansion handles may be configured to expand or collapse the tree diagram at the node they are adjacent to. The expansion handles may optionally be configured to display or hide selected of the auxiliary nodes.

Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.

Abstract: A method and structure for an independent programming tool for analyzing business separations-of-duties conflicts for users and profiles in an object-oriented application, the tool including a database containing a matrix of transactions, descriptions, object authorization values, and transactional separations-of-duties conflicts; an analysis engine adapted to use data from the object-oriented application in conjunction with the matrix to analyze business conflicts and produce separations-of-duties conflict reports about the object-oriented application; and a user interface adapted to control the tool.

Abstract: Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word from the dynamic memory, to detect at least one or more unidirectional errors in the input data word read from the dynamic memory, and to generate an error signal when at least one error is detected, the error signal indicating that the input data word contains expired data. Control circuitry included in the apparatus is configured for initiating one or more actions in response to the error signal.

Abstract: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.

Abstract: A method for cleaning a semiconductor structure including providing a chamber for holding the semiconductor structure and a dense phase fluid, providing a thermal transfer device having a thermal transfer surface, connecting the thermal transfer device to the chamber, placing the semiconductor structure in the chamber in contact with the thermal transfer surface and thermally cycling the thermal transfer surface.

Abstract: Apparatus and methods are provided for thermally coupling a semiconductor chip directly to a heat conducting device (e.g., a copper heat sink) using a thermal joint that provides increased thermal conductivity between the heat conducting device and high power density regions of the semiconductor chip, while minimizing or eliminating mechanical stress due to the relative displacement due to the difference in thermal expansion between the semiconductor chip and the heat conducting device.

Abstract: The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.

Abstract: A method and system for data redundancy, wherein method comprises storing an object in an object storage device, storing a duplicate of the object in a second object storage device, converting the object into any of a grouped object Redundant Array of Independent Disks (RAID) layout and an individual RAID layout upon growth of the object, and discarding the duplicate object. The step of converting further comprises determining which of the grouped object RAID or individual RAID layout to convert the object into based on a size of the object being converted. Moreover, the step of converting into a grouped object RAID layout further comprises selecting a group based on whether the group comprises other objects similarly sized to the object, wherein the similarly sized objects comprise variably sized objects.

Abstract: A system and method is provided for displaying a selection based action bar to a user that the user is able to use to perform actions using selected data. A user selects one or more displayed selections using a selection device. After the user selections have been made, the system determines which actions can be used with the selected data. Graphical components that correspond to the allowed actions are placed in an action bar and the action bar is displayed proximate to at least one of the user's selections. The action bar is not removed and remains visible as a result of the user scrolling display or performing unrelated actions. Providing a persistent action bar in location proximate to the user's selection helps the user maintain focus on the selected data. In addition, the selection based action bar can be used as a visual placeholder are marking mechanism.

Abstract: A circuit for use in a microprocessor, comprising a 4-2 compressor circuit having a full adder formed of dual XOR/XNOR cells and a 2-1 MUX. The full adder uses minimum sized XOR/XNOR cells.

Abstract: An automated bit-sliced datapath system generating tool is built so design can be performed at a higher level, and automated generation of the synthesizable HDL representation can be accomplished are disclosed. A method defines datapath system characteristics, defines core/pin rules, and then constructs class-type inference rules that can be used for automatically generating the datapath system. An “orthogonal bundling” technique is used that groups pin by a class, and also by a channel identifier. The class-type inference rule corresponding to each class uses of the following factors to infer appropriate wiring: 1) number and type of pins in the class created by the instantiation of cores by the user; 2) attribute definitions on pins set by library core/pin rules; 3) user selection of “global attributes”; 4) user definition of channel bit order (“link orders”) to imply the order of connection between stages; and 5) user-defined attributes set on pin classes.

Abstract: A method, apparatus and program product for the dynamic reallocation of shared processing resources in a computing system is provided. The method/apparatus/program product attempts to allocate the shared processing resource among the two or more logical partitions in the computing system based on a current utilization of the shared processing resource among each of the two or more logical partitions and a current utilization of shared processing resource for the computing system as a whole. More specifically, the shared processing resource is reallocated from logical partitions having a relatively lower current utilization of their owned portion of the shared processing resource to logical partitions having a relatively high current utilization of their owned portion of the shared processing resource.

Abstract: A method, system and computer instructions for users to visually rearrange telephone call trees are disclosed. A caller can connect to an automated telephone answering service, and download the service's call tree. The caller can view a display with the call tree, and modify or rearrange the order in which the menu options of the call tree are displayed. The user can then store the modified call tree for use in the future.