Abstract: An integrated circuit chip includes multiple functional components and a central interconnect module providing communication among the functional components. The central interconnect module includes a buffer which is shared by the sending and receiving components. Preferably, some components perform different functions and communicate with the central interconnect via a common architectural interface. Preferably, each sender is allocated respective credits representing ability of the receiver to receive data (e.g., available buffer space), and the sender can transmit data if it has credits. Credits are decremented when the sender sends data, and returned by the receiver when is again able to receive. The use of a common central interconnect module with a shared buffer reduces buffer requirements and provides a low-overhead path for transferring data within the integrated circuit chip.

Abstract: A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines is selectively coupled to a common true node through an n-type pass device and a p-type pass device in parallel therewith, and each of the complementary bitlines is selectively coupled to a common complementary node through an n-type pass device and a p-type pass device in parallel therewith.

Abstract: Mechanism for accurately measuring useful capacity of a processor allocated to each thread in a simultaneously multi-threading data processing system. Instructions dispatched from multiple threads are executed by the processor on a same clock cycle. A determination is made whether Time Base (TB) register bit (60) is changing. A dispatch charge value is determined for each thread, and added to the Processor Utilization Resource Register for each thread when TB bit (60) changes.

Abstract: A customer record is generated to include fields specifying at least one product, customer preferences, and a selected delivery option indicating a method to deliver generated output material on the product. A job record including a status field is added to a job status table and set to a first status. A first worker is invoked if the selected job has the first status to generate output material from processing the product and customer preference fields in the customer record for the selected job. The status for the selected job in the job status table is set to a second status after generating the output material with the first worker. A second worker is invoked if the selected job has the second status to determine whether a selected one of a plurality of delivery options from the customer record for the selected job and transmits the output material via the determined delivery option to the customer specified in the customer record.

Abstract: A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.

Abstract: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step.

Abstract: A data mapping device, a method, and an article of manufacture for adjusting a transmission rate of ISC words are provided. The GFP data mapping device has a FIFO buffer and a transceiver operably coupled to the FIFO buffer. The method includes reading first and second ISC words from the FIFO buffer that were received from a transmitting device. The method further includes determining whether a first number of ISC words stored in the FIFO buffer are greater than a second predetermined number indicating an over-running condition. The method further includes determining whether the first and second ISC words indicate either an ISC continuous sequence of words or an ISC idle sequence of words, if the first number is greater than the second predetermined number. The method further includes deleting the first and second ISC words if the first and second ISC words indicate either the ISC continuous sequence of words or the ISC idle sequence of words.

Abstract: The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device.

Abstract: A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, determine whether an amount of usage of a resource, which is used under a temporary usage plan, exceeds a threshold. If that determination is true, a quantity of the resource is calculated and that quantity is converted from the temporary usage plan to a permanent usage plan, without further charge to the customer. In another embodiment, a different resource may be converted to the permanent usage plan than the resource that was temporarily used. In various embodiments, the calculation of the quantity is made based on an attribute of the computer that uses the resource or based on an activation code received from the provider of the resource. In various embodiments, the amount of the usage is either a time amount of use or a monetary amount charged for the resource under the temporary usage plan.

Abstract: A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When the system clock is below a predefined frequency threshold, the reset control signal is an array tracking reset signal, wherein the active pulse width of the array clock is system clock frequency independent, and when the system clock is above the predefined frequency threshold, the reset control signal is a mid-cycle reset signal, meaning that the active pulse width of the array clock is system clock frequency dependent. A bypass signal is provided as a third input control signal, which when active causes the clock control circuit to output an array clock which mirrors the system clock.

Abstract: The invention broadly and generally provides a key for a vehicle comprising: (a) a biometric sensor operable to create a measurement of at least one biometric property; (b) a data storage device operable to store data; (c) an authenticator operable to detect existence of a specified relationship between the aforesaid measurement and data stored within the aforesaid data storage device; and (d) a communication device operable to communicate in response to the aforesaid existence of the aforesaid specified relationship.

Abstract: In a remote runtime engine, a method for debugging a remotely executing high level language specified computer program can include the steps of interpreting a high level language specified computer program and receiving debug messages from a debug tool over a computer communications network. Consequently, the received debug messages can be applied to the high level language specified computer program. Additionally, debug messages can be sent to the debug tool over the network. In a particular aspect of the invention, the method can include setting a breakpoint in the runtime engine on a method specifying logic for receiving the debug messages. Responsive to reaching of the breakpoint, the receiving and applying steps can be performed for a debug message in a message queue in the debug tool. Similarly, a breakpoint can be set in the remote runtime engine, and responsive to reaching the breakpoint, the sending step can be performed.

Abstract: A method and system obtains a linear combination in accordance with an image processing algorithm using at least one lookup table that is indexed by at least one subset of bits from a set of pixels in an image.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: The present invention provides a method, system, and computer program product for providing quality of service guarantees at the application level for clients of application servers. The method includes: receiving a request for a transaction of type k; calculating a throughput rate ?i of each type of transaction i, 1?i?n, in response to the request for the transaction of type k; calculating an average residual time Ri of each type of transaction i, 1?i?n; calculating an average residual time R of a transaction in service; calculating an average waiting time Wk of a transaction of type k; comparing the average waiting time Wk of a transaction of type k to a required average waiting time W{tilde over (k)} of a transaction of type k; and selectively accepting the request for the transaction of type k, based on a result of the comparing step.

Abstract: A method (and structure) of linear algebra processing, includes processing a (real or complex) matrix data having elements originally stored in one of a triangular format and a symmetric matrix format in a subroutine designed to process matrix data in a full format. The processing uses a hybrid full packed data structure, which provides a rectangular space characteristic of the full format. The rectangular space is defined by a leading dimension (LD). Inside of the rectangular space are stored a plurality of entities that include all elements of the matrix data originally stored in the triangular or symmetric format.

Abstract: A visual query explain mechanism displays a query to the user in a graphical tree format. A user may execute a query, and the actual performance from executing the query is imported into the visual query explain mechanism. The visual query explain mechanism adds the actual performance to the nodes in the query tree, and compares the actual performance to the estimates of performance that were generated prior to executing the query. The visual query explain mechanism then looks at a predefined threshold value, and determines whether actual performance exceeds the estimated performance by the predefined threshold value. If so, the corresponding node in the query graph is highlighted in some way, thereby providing a visual indication to the user of problem areas in the query.

Abstract: A method of forming a semiconductor device, comprising providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.

Abstract: An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions prior to the set of instructions being placed in the instruction cache.

Abstract: A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

Abstract: A method and apparatus are used for finding the longest prefix match in a variable length prefix search when searching a direct table within a routing table structure of a network processor. The search through the routing table structure is expedited by hashing a first segment of an internet protocol address with a virtual private network number followed by concatenating the unhashed bits of the IP address to the result of the hash operation to form an input key. Patterns are compared a bit at a time until an exact match or the best match is found. The search is conducted in a search tree that provides that the matching results will be the best possible match.

Abstract: A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values.

Abstract: An integrated circuit chip includes multiple functional components and a central interconnect (CI) module. Each functional component communicates with the CI module via a respective internal bus sharing a common architecture which does not dictate any particular data alignment. The chip architecture defines an alignment mechanism within the CI module, which performs any required alignment of transmitted data. Alignment mechanism design parameters can be varied to accommodate different alignment domains of different functional components. Preferably, the common bus architecture supports multiple internal bus widths, the CI module performing any required bus width conversion. Preferably, for certain transactions not containing a data address, correct alignment is obtained by placing restrictions on transaction size and boundaries, and duplicating certain data on different alignment boundaries.

Abstract: A method and service creates and maintains a virtual point-in-time copy of source data stored within a source storage unit. The method/service receives at least one request to create a point-in-time copy of the source data. However, instead of creating a copy of the source data, the invention creates a target storage unit mapping table within a target storage unit or other storage units managed by the same storage system. This target storage unit mapping table contains pointers to the source data. In addition, the invention maintains a modification space within the target storage unit or other storage units managed by the same storage system. Each portion of the modification space is associated with a given target storage unit. The modification space only stores changes to the source data that are unique to the corresponding target storage unit.

Abstract: Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.

Abstract: A method and system for managing a service level of a service provided by a service provider to a customer under a service level agreement. The actual measurement data is adjudicated to correct the measurement data in accordance with at least one adjudication element that provides information relating to how to correct the measurement data. The adjudicated measurement data is transformed into operational data by being reorganized into one or more groups of data. The operational data is evaluated by applying a formula to the operational data, resulting in the operational data being configured for being subsequently qualified. The operational data is qualified by comparing the evaluated operational data with specified service level targets for at least one service level period and identifying operational data points meeting and/or not meeting the specified service level targets.

Abstract: A method and respective system for operating a speech recognition system, in which a plurality of recognizer programs are accessible to be activated for speech recognition, and are combined on a per need basis in order to efficiently improve the results of speech recognition done by a single recognizer. In order to adapt such system to the dynamically changing acoustic conditions of various operating environments and to the particular requirements of running in embedded systems having only a limited computing power available, it is proposed to a) collect selection base data characterizing speech recognition boundary conditions, e.g. the speaker person and the environmental noise, etc., with sensor means, and b) using program-controlled arbiter means for evaluating the collected data, e.g., a decision engine including software mechanism and a physical sensor, to select the best suited recognizer or a combination thereof out of the plurality of available recognizers.

Abstract: Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to Writing the branch into a Level 1 (L1) cache to provide a pre-decoded branch, and then writing the pre-decoded branch into the L1 cache. By pre-calculating matters relating to the targets of branches before the branches are written into the L1 cache, for example, by re-encoding relative branches as absolute branches, a reduction in branch redirect delay can be achieved, thus providing a substantial improvement in overall processor performance.

Abstract: A method, system, and computer program product for transferring N table instances X1, X2, . . . , XN of a table T from a source database S to destination databases D1, D2, . . . , DN, respectively. The method is implemented by executing a computer code by a processor of a computer system. N is at least 1. For I=1, 2, . . . , N the method includes: determining whether the table T has been defined for destination database DI, and if it is determined that the table T has not been defined for the destination database DI, then defining the table T for the destination database DI; and transferring the instance XI of the N table instances from the source database S into the defined table T of the destination database DI.

Abstract: An interactive presentation environment for eMeetings or the like that provides participants with more control over what they see and hear. One embodiment of the interactive presentation environment comprises a meeting recorder adapted to create a recording of a live meeting and a navigation control for selecting a portion of the recording to view during the live meeting. Some embodiment may further comprise a timeline control containing a first graphical indicator associated with a live position and a second graphical indicator associated with a current position, a bookmark control adapted to mark a portion of the recording for archiving, and a display operatively connected to the meeting recorder and the navigation control.

Abstract: A precision voltage reference for ultra-thin gate oxide process technologies is realized with a network of tunneling current circuit elements. A voltage difference is measured between selected nodes of one or more current paths of a voltage divider. The tunneling current circuit element may be implemented with any suitable device, such as a parallel plate capacitor or MOSFET. The physical properties of gate tunneling currents enable the voltage reference output to be largely independent of temperature. The circuit may be implemented for low voltage operations with input power supply values of 1.2 volts or less. The output voltage tolerance may be designed to be about ±25% or less of a power supply voltage tolerance. In addition, variations in gate oxide thickness account for a change of less than about ±2% in the voltage reference generator output.

Abstract: The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

Abstract: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC?expB+CV).

Abstract: An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.

Abstract: An extensible identification system for nodes in a hierarchy is described wherein each node is assigned a concatenation of decimal based values. The values assigned uniquely identify the node, provides an order for the node, and identifies its parent, child, and sibling relationships with other nodes Furthermore, the IDs assigned can be encoded to be byte comparable. Furthermore, the ID's assigned to nodes need not be modified when changes (adding/deleting a child node or a subtree of nodes) are made in the hierarchy. Additionally, in the event of such a change, the order and relationships between the parent, child, and sibling nodes are retained.

Abstract: Disclosed are methods and systems for expanding the search space in a Peer-to-Peer (“P2P”) network. In one embodiment, the search space is expanded by increasing the time-to-live value of the search request message. The P2P network may include a plurality of nodes, and the method for increasing the search space in the network includes the steps of receiving a search request message; changing a time-to-live value carried by the message; and forwarding the message to at least one peer node.

Abstract: An apparatus, program product and method improve management of available computing resources by adjusting use of the resource over a first interval according to actual use of the resource during a second interval. This feature enables a computing resource to exceed its normal limits during the first interval of operation. Use during the second interval may be limited to balance out the burst, or excessive resource usage of the first interval.

Abstract: A system and method are provided for monitoring temperature within a specified integrated circuit. Usefully, the system comprises at least one oscillator device proximate to the integrated circuit for generating signal pulses at a frequency that varies as a function of the temperature adjacent to the oscillator device. The system further comprises a control unit for establishing sample acquisition periods of invariant time duration based on an time invariant reference clock. A sampling component is coupled to count the number of pulses generated by the oscillator device during each of a succession of the time invariant sample acquisition periods, and a threshold component responsive to the respective count values for the succession of sample acquisition periods provides notice when at least some of the count values have a value associated with a prespecified excessive temperature level.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, adjust a resource capable of being activated at a computer based on whether the elapsed time since the manufactured date of a computer is greater than a threshold. The threshold may be fixed or variable. In various embodiments, the adjusting may increase the amount of the resource capable of being activated, increase a time period during which the resource is capable of being activated, or decrease a price charged for a monitored resource. The type of the adjusting is chosen based on the type of the on-demand capacity plan in which the resource is enrolled. In this way, the resources activated for use, the cost of the activated resources, and/or the time periods in which resources are activated may be more easily adjusted.

Abstract: A memory controller utilizing a performance monitor to modulate the level of data security applied to the data being transferred to and from memory depending on the performance. The performance monitor tracks the response time for access to the memory over a defined time window. The response times are then compared to a predefined allowable response time. This comparison is done over a predefined window of time. When the actual response times exceed the allowable limits, the level of encryption is limited until performance parameters fall within the limits selected. The frequency with which the encryption mechanism is adjusted may also be predefined. Data transfers continue as the controller monitors system performance and controls the level of security applied to the data according to that performance data. The performance modulation can be different depending on what unit is accessing memory in multi-unit systems.

Abstract: The present invention is a method and apparatus for the detection of portable electronic device functionality. In a preferred embodiment, the present invention includes a chemically coated antenna to serve as a trigger for device functionality detection. The chemically coated antenna may be passively or actively detected. In active detection, a detection apparatus releases a chemical which reacts or otherwise respods with the chemical trigger in a detectable manner. The detection apparatus detects the reaction, which is specific to the functionality of the portable electronic device. In passive detection, a detection device simply detects the chemical trigger, which is specific to the portable electronic device functionality. Other trigger embodiments utilizing optics, radio frequency (RF) signals, sound waves, and magnetic identification are also disclosed.

Abstract: Towards mining closed frequent itemsets over a sliding window using limited memory space, a synopsis data structure to monitor transactions in the sliding window so that one can output the current closed frequent itemsets at any time. Due to time and memory constraints, the synopsis data structure cannot monitor all possible itemsets, but monitoring only frequent itemsets makes it difficult to detect new itemsets when they become frequent. Herein, there is introduced a compact data structure, the closed enumeration tree (CET), to maintain a dynamically selected set of itemsets over a sliding-window. The selected itemsets include a boundary between closed frequent itemsets and the rest of the itemsets Because the boundary is relatively stable, the cost of mining closed frequent itemsets over a sliding window is dramatically reduced to that of mining transactions that can possibly cause boundary movements in the CET.

Abstract: An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions are part of a group including a prior set of instructions received in the instruction cache including using a history data structure, wherein the history data structure contains data regarding instructions in the prior set of instructions. Any instructions are grouped into the group with the instruction in response to a determination that the any instructions are part of the group. Instructions in the group units are dispatched to execution using the history data structure, wherein invalid instruction dispatch groupings are avoided.

Abstract: A system and a method for initializing a communication link for transmitting a data stream from a first computer through a synchronous optical communication network to a second computer are provided. The method includes transmitting a first request message in a first GFP data frame to a second computer. The method further includes transmitting a second acknowledgement message in a second GFP data frame from the second computer to the first computer. The method further includes initializing the communication link between the first computer and the second computer in response to the acknowledgement message.

Abstract: An integrated circuit (IC) chip (100) containing a plurality of voltage islands (124I-M) containing corresponding functional blocks (104I-M) that can be selectively fenced, i.e., powered down, while saving the states of the corresponding inputs, and unfenced in order to manage power consumption of the chip. Each fencable functional block includes a power switch (140I-M) and state-saving circuitry (148I-M) for saving the state of the inputs to that functional block. A power modulation unit (PMU) (132) generates fencing signals (144I-M) that control the power switches and state-saving circuitries so as to selectively fence the corresponding functional blocks. The PMU generates the fencing signals as a function of one or more operating arguments.

Abstract: A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.

Abstract: An application server includes a connection pool that specifies a number of allowable connections, and includes a backend failure detection mechanism and a backend failure recovery mechanism. When the backend failure detection mechanism detects that the backend fails, applications waiting on the hung connections may be notified of the backend failure. The backend failure detection mechanism will then detect when the backend recovers and becomes available once again. Once the backend is available again, the backend failure recovery mechanism increases the number of connections in the connection pool to compensate for the hung connections. As each hung connection is timed out using a network timeout mechanism, the number of allowable connections is reduced. Eventually all of the hung connections will time out, with the result being that the connection pool will contain the same specified number of allowable connections it originally had before the backend failed.

Abstract: A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.

Abstract: A method, apparatus and program product for focusing the display of tabular data wherein the display has multiple rows and columns of cells. A computer running a tabular data application includes a display for displaying the tabular data. The tabular data application includes a routine for defining a user defined area in the tabular data display in a focused display. The routine places indicators at the top, bottom, right side and left side of the focused display. The indicators may be one of an expand indicator or a collapse indicator. A movable cursor in the tabular data display is used to select at least one of the indicators for focusing the display. The routine in the tabular data application expands or collapses the display of tabular data to give a focused display. The expanding or collapsing of the display is determined by whether the selected indicator is an expand indicator or a collapse indicator.