Abstract: A semiconductor device including a conductive substrate, an insulator layer, a silicon layer doped with impurities and forming a first transistor and a second transistor, an isolation volume between said first transistor and said second transistor, and a conductive stud extending from the doped silicon layer to the substrate.

Abstract: An improved, high performance differential voltage regulator for high capacitance loads using a transistor-capacitor that will, while operating with voltages below 5 volts, have wide bandwidth, high current, and loop stability over a to a wide range of output capacitive loads.The regulator achieves this through first and second control loops coupled to a first one of a pair of differential transistors 2.

Abstract: An improved multiple bus system for a multiprocessor computer system is disclosed for a computer system having a multiple level cache memory structure. The system includes one or more logical busses each including two or more physical busses for coupling multiple processors to a memory unit. Each logical bus is coupled to a bus switching unit which in turn couples all of the processors in the multiprocessor system to a memory unit over the physical busses comprising the logical bus. The system further manages near end signal reception problems caused by multiple processors electrically interconnected over such a bus system.

Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

Abstract: Integrated circuit chips (18, 42, or 56) are packaged within openings formed in a substrate such as PCMCIA Card (20, 40, or 54), thus allowing compliance with overall width dimension requirements for standardized electronic components. The arrangement has the advantages that thermal coefficient of expansion of the chips and cards match, and that a sturdy, multilayer ceramic substrate is used for electrical connection to electronic devices such as laptops, palmtops, and the like. In addition, a second integrated circuit chip (68) can be connected directly to the embedded chip (56), thereby allowing two chips to be accommodated in a card (54) at the same location and allowing chip-to-chip electrical communication. A variety of electrical bonding methods joining the embedded chip to the card can be employed. In addition, a variety of thermal conduction arrangements can be used for cooling the embedded integrated circuit chip.

Abstract: A computer system having multiple floating point modes and common instructions for each mode in order to implement operations in a mode independent manner. A computer system includes two floating point modes supported by a common set of instructions for implementing operations, said instructions thereby being mode independent. The computer system includes a means for storing information for specifying the current floating point mode; and a floating point unit adapted to execute any one instruction from among the common set of instructions in accordance with the stored rounding mode and the operation associated with said instruction, thereby providing for mode independent operation. In an embodiment of the present invention, the floating point mode is either binary floating point or hexadecimal floating point.

Abstract: A development tool simplifies layout of a part for a multimedia title. A spacer tool may be placed onto a graphical representation of a part. The spacer tool may be a play spacer which plays the part for a designated period of time, a hide spacer which hides what would have been an otherwise visible portion of a part, a rate spacer which changes the rate at which the part is played, or a move spacer which causes a part to move along a predetermined path while visible.

Abstract: A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.

Abstract: An electronic package is fabricated by providing a thin, circuitized substrate having electrical circuitry on a first surface; and then molding a dielectric body to the first surface of the substrate. The dielectric body contains an opening for exposing a portion of the surface of the thin circuitized substrate having at least a portion of the electrical circuitry. A semiconductor device is then positioned within the opening of the molded dielectric body and is electrically coupled to at least a portion of the electrical circuitry on the exposed portion of the surface of the thin circuitized substrate. Next, a plurality of electrical conductive members are secured to a surface of the thin circuitized substrate that is opposite the first surface.

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten.

Abstract: A document can be collaboratively edited by multiple editors by providing each editor with a separate copy of the document. Each editor then edits his own document copy using an editing application program, such as a word processor, to produce an edited copy. The edited copies are then retrieved and compared and a single marked-up document is created in which sections (for example, paragraphs) of the original document and corresponding sections of each of the edited documents (with changes from the original document indicated) are displayed in physically adjacent locations of the display screen. The displayed sections contain both edited and duplicated, unedited text. A set of "consolidation" tools are provided to quickly transfer edits between the physically adjacent areas of the screen and to make, or accept, edits made by any of the editors. A final document copy is made by eliminating the duplicate text in the sections.

Abstract: This invention relates to the use of water-based cleaning solutions and their use as environmentally safe replacements of chlorinated hydrocarbon solvents to remove metal-polymer composite paste residue from screening masks and ancillary equipment, such as, used for screening a conductive metal pattern on a ceramic green sheet in the manufacture of multi-layer ceramic products.

Abstract: A passive radio frequency transponder (RF tag) having a diode rectifier receiver circuit outside the tag power rectification circuit, the tag power rectification circuit supplying power to the electronics of the RF tag. An additional innovative low current circuit protect the signal capacitor from overvoltage produced by the signal diode. An innovative circuit also clips the signal and sharpens it. An innovative low current circuit is used as a comparator to sharpen the signal pulses.

Abstract: A very long instruction word (VLIW) architecture and method provide for functionally expanding a parcel. The instruction register of the VLIW architecture is divided into a plurality of parcels, each of which has corresponding processing logic. The processing logic performs various functions based on the data within the corresponding parcel. A single parcel, however, can only specify a limited number of functions or include a limited amount of data for processing such that the level of optimization for a given VLIW may be impeded. The selector logic and processing logic, however, allow for data from a non-corresponding parcel to be selected and processed. In this manner, the functions and/or amount of data for processing in a single parcel can be expanded by using data from a non-corresponding parcel.

Abstract: A disk drive or comparable device is described which has two microprocessors connected by a communication link. One of the microprocessor accesses nonvolatile storage means containing object code in a compressed format for the other microprocessor. When the device is reset the microprocessor having access to the ROM decompresses the object code and transmits it to the second microprocessor. The compression scheme stores indexes into a table for the N most frequent words in the object code and leaves any excess words uncompressed. The uncompressed words are distinguished from the indexes by a set of flags which may be stored in-line with the compressed code or stored separately to avoid having to perform bit shifting to restore elements to byte boundaries.

Abstract: The present invention is a method of providing a protective covering on an electronic package including a first circuitized substrate, a semiconductor chip positioned on and electrically coupled to the first substrate, and a plurality of conductors also on the substrate for electrically connecting the substrate to an external circuitized substrate. In one version, the method comprises covering substantially all of the external surfaces of the substrate, the semiconductor chip and a portion of the plurality of conductors with a protective covering from immersion in a dielectric solution (e.g., TEFLON AF). The coatings can also be applied by brushing, spraying, or chemical vapor deposition. In an alternative embodiment, all of the external surfaces, including all of the conductors, are coated with the protective covering (e.g., to facilitate package shipment or other handling). The resulting electronic packages are also described herein.

Abstract: According to the preferred embodiment, a defect monitor is provided that uses a floating gate structure. The defect monitor includes a common source, a common drain, and a plurality of floating gates interdispersed between the source and drain. Additionally, a conductor covers the plurality of floating gates. By applying a bias to the conductor and measuring the current flowing through the drain and source, the distribution of defects on the semiconductor wafer can be estimated.

Abstract: An interleaved data cache array which is divided into two sub arrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a first content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addresssable fields for the effective address and real address offset and alias problems may be efficiently resolved. A virtual address aliasing condition is identified by searching each cache line for a match between a portion of a desired effective address and the content of the first content addressable field.

Abstract: A multiprocessor computer system comprises a plurality of processors, wherein each processor includes an execution unit, a program counter, a result buffer containing a plurality of entries, each entry being allocated to hold an output value of an instruction executed by the execution unit, and an operation counter containing an operation count that is incremented at least when an instruction storing an output value to the result buffer is executed by the execution unit. A particular entry allocated in the result buffer for a given output value is selected as a function of the operation count at the time the instruction generating that given output value is executed. Each processor further includes a decoder that extracts a processor identifier from an instruction to be executed that identifies one of the plurality of processors, wherein one or more input values of the instruction are retrieved from the result buffer of the identified processor.

Abstract: Disclosed is a method and system for performing a partial-sum query in a database in which the data is represented as a multi-dimensional data cube. The data cube is partitioned into multi-dimensional blocks. One or more covering codes are then selected for each block, and a group of partial-sums is computed for each block based on its covering codes. At query time, the query result is generated by combining the partial-sums for those blocks that intersect with the query subset. To improve the query response time and reduce system storage requirements, the covering codes are preferably augmented as single-weight extended covering codes or composition-extended covering codes. Also, a second partial-sum may also be computed for each block to efficiently find its partial sum, based on the block's first partial-sums and the bit-position differences between selected codewords for the block and bit strings representing the cell indexes of the blocks intersecting with the query subset.

Abstract: Method and system aspects output a single audio stream from a plurality of audio streams provided by at least one application program running on a computer system with an audio device. Production of the single audio stream includes forming a server process in the computer system, emulating the audio device with the server process to allow any combination of audio stream formats, and manipulating the plurality of audio streams with the server process to form the single audio stream for maintaining transparency to the at least one application program.

Abstract: A single file holds multiple versions of a document composed of an interconnection of objects which themselves have versions and are stored in the file. When the document is changed by changing any of the interconnected objects, a check is first made to determine whether the object version is same as the document version currently being edited. If not, a copy of the object is made and saved. Any version of the document can be reconstructed by interconnecting object versions which have a highest level which is equal to, or less than, the desired document version. Therefore, only objects which are changed are duplicated and copies of objects are only made when an object changes. The interconnection of the objects to form structure of the document is maintained by an interconnection of object pointers. Each object has an associated demand loader object which includes a list of object versions for the associated object plus a pointer to one of the versions.

Abstract: A stiffener (34 or 52 or 72) includes a pathway which allows gases and fluids, such as air, to be vented from the interface between surface bonding regions (35 or 60 or 74) of the stiffener and an adhesive (38 or 56 or 80) on a flexible substrate (36 or 54 or 78). The pathway may take the form of a porous material used for the stiffener or one or more bore holes (58 or 59 or 70) formed in the stiffener. The stiffener may also include an internal cavity (76) for promoting venting of fluids and gases. By venting fluid and gases from the adhesive/stiffener interface, better adhesion between the stiffener and flexible substrate is achieved.

Abstract: A versioned-data management system (VDMSMS) is provided with a method for determining candidates for promotion in association with a user task. The VDMS maintains a list of parts changed as a result of a user task, referred to as a promote group. Before performing any changes the user informs the VDMS which user task is to be associated with the changes. All parts subsequently changed are automatically placed by the VDMS in the promote group associated with the given user task. When the parts associated with a user task for a given variant level are promoted, an iterative process is performed to determine the complete set of parts that must be promoted in support of the requested promote. Initially the set includes those parts in the promote group at the given variant level. Then all the other promote groups are searched to determine whether they contain any of the parts at the given variant level that are already in this set.

Abstract: A software class including known system events is imported into the palette of a development tool. After selecting a class for import, all variables and methods in the class meeting predetermined criteria are discovered. The variables are marked as properties, the methods as actions and the system events as events. A capture method is generated to capture the events and forward them to the development tool. Then, an invoke method is generated to execute each of the actions, a set method is generated to set a value for each of the properties, and a get method is generated to retrieve each value. Finally, a new subclass comprising the capture method, the invoke method, the set method and the get method is generated and added to the palette.

Abstract: A display device includes field emission cathode apparatus for emitting electrons. A plurality of electron beams are formed from the field emission cathode apparatus. A screen, which has a phosphor coating facing the cathode receives the plurality of electron beams. The phosphor coating includes a plurality of pixels each corresponding to a different one of said plurality of electron beams. A grid electrode is disposed between the cathode and the screen for controlling the flow of electrons from the cathode. The field emission cathode includes extractor grid means, having a plurality of separately addressable portions associated with each of said plurality of pixels. A gamma transfer function between input data value and beam current is provided in order to emulate a conventional CRT. This can be achieved by use of a lookup table.

Abstract: An integrated circuit includes a digital bus providing a first portion of less significant signals, and a second portion of more significant signals. A digital-to-charge converter connected to the digital bus includes circuitry to convert the less significant portion of the signals to a first charge, and to convert the more significant portion of the signals to a second charge. A charge-to-voltage converter connected to the digital-to-charge converter includes circuitry to convert the first charge to an intermediate voltage. A voltage-to-charge converter connected to the charge-to-voltage converter converts the intermediate voltage to a third charge. A charge-summer connected to the digital-to-charge converter and the voltage-to-charge converter combines the second charge with the third charge to produce a combined charge. The charge-to-voltage converter also is connected to the charge-summer to convert the combined charge to an analog output voltage.

Abstract: A method to construct a global equivalent database log file that transforms local log files from a parallel or distributed database system by extracting from each log file sequences of log entries from each database record, breaking the sequences into a series of segments, discarding the bulk of the segments and shortening other segments, then merging the remaining segments into an equivalent log file. The sequences are called "UID-sequences" and the segments "UID-segments" because they relate to one unique record ID or UID. The method also employs backward and forward superposition to further shorten the segments. This method works on database systems with or without instant constraint checks and also provides for treating log entries from multiple adjacent transactions on a log file as a single transaction. In systems with instant constraint checks, this method performs a "unique-key check" and a "foreign-key check" and resolves conflicts that are created because of superposition.

Abstract: A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Abstract: The present invention is a method of controlling a robotic mechanism comprising both active and passive joints, where the motion of one or more of the passive joints is constrained by one or more constraints imposed on the mechanism by the environment, the mechanical construction of the mechanism or the nature of the task. The method is capable of controlling mechanisms with multiple sets of passive joints with multiple environmental constraints restricting the motion of the mechanism. In a preferred embodiment the novel method is used to control a surgical robot holding a surgical instrument inserted into a patient through a natural or man-made orifice.

Abstract: This apparatus and method controls and limits the flow of in-rush current to a peripheral device coupled to a main power supply unit through a power bus and a ground bus. The apparatus and method essentially isolate and limit in-rush current flow to a capacitive load until operational current flow occurs to the peripheral device. A switching device is coupled to the power bus and the ground bus through a load. A resistive device is coupled to the power bus and the ground bus through the load. A control circuit is connected to the switching device. During initial start-up or "hot plugging" of the device, the control circuit turns "off" the switching device causing the load to be charged from the power bus through the resistive device until a predetermined condition occurs whereupon the switching circuit is turned "on" to bypass the resistive device and connect the load and the peripheral device to the power bus.

Abstract: A method for fabricating a chip carrier and attaching the chip carrier to a printed circuit board is disclosed. A plated through hole (PTH) is formed through a chip carrier substrate. The PTH has surface lands on opposite surfaces of the substrate. Next, at least one of the surfaces of the substrate is covered with a dielectric material. The dielectric material at least partially fills the PTH. A solder ball is attached to the surface land on the opposite side as the dielectric material. Then, a printed circuit board is positioned relative to the chip carrier such that the solder ball contacts a surface land of the printed circuit board. Then, the solder is reflowed. Because the solder is reflowed while the dielectric material at least partially fills the PTH, the dielectric material within the PTH prevents the solder from flowing entirely through the PTH. This prevents contamination of the opposite surface of the chip carrier.

Abstract: Disclosed is an automatic container assembler apparatus (800) to assemble the constitutive elements of a COAST container i.e. the wafer (138) that is to be treated in the manufacturing line, the cassette-reservoir (123) and the single wafer holder (130). In essence, the assembler apparatus consists of a cabinet whose interior space cabinet is submitted to a clean filtered gas flow generated by a blower, so that a clean gaseous mini-environment is created therein with a light overpressure with regard to the outside ambient. The cabinet includes a vertical stocker (804) adapted to be manually and safely filled with the adequate number of the elements mentioned above. Generally, the wafers are carried in a multiple wafer holder (130'). These elements are introduced in the cabinet through an input loadlock device (810) and laid down onto a table (806) by an operator. Next, the operator places them in their respective bins (815) of the stocker through manipulation gloves (805).

Abstract: High quality factor (Q) spiral and toroidal inductor and transformer are disclosed that are compatible with silicon very large scale integration (VLSI) processing, consume a small IC area, and operate at high frequencies. The spiral inductor has a spiral metal coil deposited in a trench formed in a dielectric layer over a substrate. The metal coil is enclosed in ferromagnetic liner and cap layers, and is connected to an underpass contact through a metal filled via in the dielectric layer. The spiral inductor also includes ferromagnetic cores lines surrounded by the metal spiral coil. A spiral transformer is formed by vertically stacking two spiral inductors, or placing them side-by-side over a ferromagnetic bridge formed below the metal coils and cores lines. The toroidal inductor includes a toroidal metal coil with a core having ferromagnetic strips. The toroidal metal coil is segmented into two coils each having a pair of ports to form a toroidal transformer.

Abstract: An apparatus and method for reducing spindle power and acoustic noise in a self-commutating brushless d.c. motor for a disk drive adjusts the commutation angle of the motor until a point of optimum power consumption is reached. In a preferred approach implemented during disk drive operation, a direction in which to change the commutation angle is determined such that spindle power consumption is decreased. The commutation angle is the changed in the determined direction until a point of minimum spindle power consumption is identified. In order to determine the correct direction of commutation angle change, the commutation angle is varied in a first direction for so long as the spindle power consumption is decreasing. If varying the commutation angle of the motor in the first direction results in an increase in spindle power consumption, the commutation angle of the motor is varied in a second direction.

Abstract: A method of forming interlevel studs in an insulating layer on a semiconductor wafer. First, a conformal BPSG layer is formed on a Front End of the Line (FEOL) semiconductor structure. Vias are opened through the BPSG layer to the FEOL structure. A layer of poly is formed (deposited) on the BPSG layer, filling the vias. The poly layer may be insitu doped poly or implanted after it is deposited. The wafer is annealed to diffuse dopant from the poly to form diffusions wherever the poly contacts the substrate. A non-selective slurry of colloidal silica and at least 1% ammonium hydroxide is used to chem-mech polish the poly from the BPSG layer and, simultaneously, planarize the BPSG layer.

Abstract: A method of isolating scan paths in an integrated circuit to reduce the RC delay associated with the scan paths and reduce power consumption, and to further enhance the capacitive decoupling of the power supply to reduce noise. The scan path can be connected to a data-storage element (latch or flip-flop) by a CMOS transmission gate, a single PMOS or NMOS transistor, or a logic gate (such as a NAND gate). The data-storage element is tested using either a scan-enable line, or the scan clock which is also connected to the data-storage element as an input. When the scan-enable line (or scan clock) is turned on, the scan path is connected to the output of the data-storage element.

Abstract: An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

Abstract: Two or more user applications executing on one or more processors, each controlled by an operating system, share use of a list and subsidiary list structure within a Structured External Storage (SES) facility to which each processor is connected. One of the applications registers interest in particular state transitions affecting one or more subsidiary lists within the list structure, causing a process within the SES to notify the appropriate processor when a list operation causes the particular state transition, without interrupting processing on the processor. The application receives notice of the state transition by periodically polling a vector within the processor, or by receiving control when a test by the operating system of a summary indicator for the vector causes an application exit to be driven.

Abstract: A redundant disk storage system having data stored on one disk and identical data on second disk, wherein the data stored on the second disk is in a different radial location determined by an offset. The offset could be such that the data on the first disk is stored near the inner circumference and the identical data is stored on the second disk near the outer circumference. Moreover, a RAM associated with each disk drive which stores the address and offset eliminates a RAM in the main disk controller.

Abstract: Response time jitter for high priority commands in a multimedia datastreaming system is bounded by issuing only non-blocking I/Os and by limiting the number of concurrent SCSI bus commands. A device driver in the system bounds the maximum time a VCR command must wait after it is released from a VCR queue by limiting the number of I/Os on the bus to a predetermined number functionally related to the magnitude of jitter permitted in the deterministic response requirement, and the time required for each data I/O to be issued to the decoder card. The number is such that the I/Os may issue within the jitter time with enough time remaining for issuance of a high priority VCR I/O. By limiting the I/Os to a predetermined number, the I/Os issued are constrained to be non-blocking to avoid hanging the I/O scheduler when a deterministic hhigh priority command arrives.

Abstract: A method, apparatus and article of manufacture is disclosed for eliminating periodic noise detected by a magnetic read head. In particular a time varying signal electrical signal is provided by a magnetic read head. The signal is sampled and stored in memory. Samples known not to contain a desired signal are used to extract a waveform representative of a single period of periodic noise. The representative waveform is synchronized with samples containing the desired signal and used to compensate the samples containing the desired signal in order to minimize, reduce, cancel or remove the effects of the periodic noise on samples containing the periodic noise. The compensated samples are then processed to obtain information from the desired signals.

Abstract: An apparatus for polishing a semiconductor wafer is provided which includes a wafer carrier having on its lower surface a non-uniform surface structure means to vary the force against a wafer during a polishing operation so that the polishing is enhanced and imparts a planar surface across the polished wafer. Preferred non-uniform surface structure means include use of a wafer carrier having on its lower surface a backing film having a first central portion having a predetermined compressibility and a second peripheral portion having a different compressibility than the first portion. Another non-uniform surface structure means to vary the force against the wafer comprises a wafer carrier having on its lower surface a raised circumferential region around the periphery of the carrier.

Abstract: An apparatus and method provide deposition on a surface by angled sputtering using a collimation grid having angled vanes which limit the distribution of trajectories of particles in at least one coordinate direction around a central axis oriented at an angle of less than 90.degree. to said surface; resulting in improved uniformity of deposition and/or selective favoring of deposition on surfaces at a high angle to the deposition surface (e.g. sidewalls). Substantially parallel orientation and uniform spacing of the sputtering target and deposition surface provides good uniformity of results over the deposition surface. The angled trajectories of sputtered particles provides improved deposition on sides of upstanding mandrel features and filling of recessed features of high aspect ratio, especially when the collimation grid is rotated about an axis generally perpendicular to the deposition surface.

Abstract: A method of efficient computation of gradients of a merit function of a system includes the steps of: specifying at least one parameter for which the gradients with respect to the at least one parameter are desired; specifying the merit function of interest in terms of observable measurements of the system; either solving or simulating the system to determine values of the measurements; expressing the gradients of the merit function as the gradient of a weighted sum of measurements; forming an appropriately configured adjoint system; and either solving or simulating the adjoint system to simultaneously determine the gradients of the merit function with respect to the at least one parameter by employing a single adjoint analysis.

Abstract: A method and system provide for selectively distributing communications between an application and multiple servers, allowing cooperative use of a single copy of an application. The system is situated between an application and the multiple servers. Requests from the application, responses to the requests, and events from the multiple servers, are managed in such a way that each server believes it is connected directly to the application and the application believes it is connected directly to a single server. The requests are categorized and distributed to the servers based on the type of request. The responses to these requests may be sent to the application or discarded based on the type of request and the role of the server sending the request. The events are also categorized and, based on the role of the server causing the event, they may be passed on to the application or discarded.

Abstract: Instructions are scheduled for execution by a processor having a lookahead buffer by identifying an idle slot in a first instruction schedule of a first basic block of instructions, and by rescheduling the idle slot later in the first instruction schedule. The idle slot is rescheduled by determining if the first basic block of instructions may be rescheduled into a second instruction schedule in which the identified idle slot is scheduled later than in the first instruction schedule. The first basic block of instructions is rescheduled by determining a completion deadline of the first instruction schedule, decreasing the completion deadline, and determining the second instruction schedule based on the decreased completion deadline. Deadlines are determined by computing a rank of each node of a DAG corresponding to the first basic block of instructions; constructing an ordered list of the DAG nodes in nondecreasing rank order; and applying a greedy scheduling heuristic to the ordered list.

Abstract: A shared queue is provided to allow any of a plurality of systems to process messages received by clients of a data processing environment. A received message is enqueued onto the shared queue. Any of the plurality of systems having available processing capacity can retrieve the message from the shared queue and process the message. A response to the message, where appropriate, is enqueued onto the shared queue for delivery back to the client. A unique list structure is provided to implement the queue. The list structure is comprised of a plurality of sublists, or queue types. Each queue type is divided into a plurality of list headers. List entries, containing data from the received messages, are chained off of the list headers. A common queue server is used to interface to the queue and to store messages thereon. The common queue server stores message data in storage buffers, and then transfers this data to the list entries. Thus, common queue server coordinates the enqueuing of data onto the shared queue.

Abstract: The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a queue, determining validity of the source information, and issuing the instruction for execution in response to the source information validity.

Abstract: A method and system for expanding the load capabilities of a bus, such as the PCI bus. The system includes a primary bus, a plurality of secondary buses for connecting additional devices, a plurality of in-line switches, an arbiter, and control logic means. The plurality of in-line switches are used for connecting the primary bus to a corresponding one of the secondary buses, each one of the switches having an enable line for receiving a signal to enable or disable the switch. The arbiter is used for receiving requests for control of the primary bus, and for selecting one of the requests as a master for the control. The control logic means is used for enabling and disabling each of the switches, via the corresponding enable line, for connection or disconnection to the primary bus.