Abstract: A speech recognition apparatus makes a preliminary selection of a number of candidate words from a vocabulary of words, one of which candidate words is most likely the spoken word to be recognized. For the preliminary selection, each candiate word is divided into first and second portions. For each portion of a word, there are stored probabilites of producing each label of a label alphabet during the utterance of that portion of the word. The speech to be recognized is also divided into first and second portions. A label string representing the speech to be recognized is generated, such that labels occur during the first or the second portion of the speech (or during a transition between the first and second portions. To determine the likelihood that the spoken word represents a word from the vocabulary, each label occurring during the first portion is assigned its "first portion" probability. Each label occurring during the second portion is assigned its "second portion" probability.

Abstract: In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed for a particular cycle, because in one cycle the B-to-A/C clocking that naturally occurs provides a minimum test window TP for performance and transition fault testing. Thus, less sophisticated scan test equipment can now provide both transition fault and stuck fault testing, without an increase in complexity or expense.

Abstract: An AND gate includes first and second opposite-type field effect transistors, each including first and second conduction path terminals and a control electrode. The gate's output terminal is connected, in common, to the second conduction path terminals of the transistors. A first logic input is connected to the first conduction path terminal of the first transistor and a second logic input is connected in common to the control electrode of the first transistor and to the first conduction path terminal of the second transistor. A third logic input is applied to the control electrode of the second transistor. In a standby state prior to the application of logic signals all three logic inputs are in the same state. This assures no conduction of logic signals, while conditioning the gate for rapid selection when logic signals are applied. Subsequently, logic signals are applied to the inputs with the third input being the complement level of the logic signal on the first input.

Abstract: Encryption and decryption mechanisms at transmitters and receivers, respectively, have applied thereto encryption or decryption keys and initializing values. These mechanisms generate cryptographic bit streams which are intermediate streams of generated values. These intermediate streams, generated prior to their real time need in the encryption or decryption processes, are stored in buffers until data is presented for encryption or decryption, at which time the cryptographic bit streams are conveyed from the buffers to mathematical functions, for combination with the data. This avoids the delays associated with the real time generation of the cryptographic bit streams during the encryption and decryption processes. Appropriate synchronization of the generation and buffer storage of the cryptographic bit streams at the transmitter and receiver is provided.

Abstract: Apparatus for selectively reinking an endless ribbon in that portion of the ribbon known as the ribbon print track. The ribbon print track is created in an endless ribbon by the repeated striking of the ribbon by a print mechanism thereby deforming the ribbon and depleting it of ink. Reinking the entire ribbon uses more ink than is necessary. Reinking only the print track extends the life of the ribbon by selectively using the available supply of ink. The apparatus achieves this result by use of an ink reservoir which supplies ink to a drive roller, which through a rotating pinching movement in cooperation with another roller, advances a ribbon into a stuffing cavity of an ink cartridge. The ink reservoir is rotatably mounted and formed to apply ink only to that portion of the drive roller which corresponds to the print track of the ribbon.

Abstract: A method for storing into a non-EX cache line in a multiprocessor system. Upon a store into a non-EX line the instruction execution and the processing of subsequent instructions will continue. The results of the current instruction, however, and any subsequent instruction whose decode and execution depends upon the result of the current instruction or that requires operand fetches, will not be released until the processing of the current instruction is resolved. The request to store into the non-EX line is simultaneously sent to the SCE to obtain the EX state for the line. The SCE serializes storage requests. When a request for EX state is processed, certain XI actions (e.g. XI-invalidates) may be invoked. Any instruction using fetched data XI-invalidated before the resolution of a preceding store at the same CP is considered likely to be invalid, and redone.

Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall.In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls.

Abstract: Dicyanato diphenyl fluorinated alkane resin precursor compositions are modified by the addition of minor predetermined amounts of aromatic diepoxides having high epoxide equivalent weights in order to reduce the curing temperature of prepregs and laminates, such as circuit boards, while retaining low dielectric constants, heat stability and high flame retardance.

Abstract: Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.

Abstract: A cold plate and an integrated circuit cooling module embodying a cross-hatch coolant flow distribution scheme. Cross hatch flow distribution is achieved by way of two sets of channels which run perpendicular to each other. The first set of channels is formed on a base plate. The second, perpendicular set is includes a set of inlet channels and a set of interleaved outlet channels formed on a distribution plate. In the preferred embodiment, the base and distribution plates are separated by an interposer plate that has nozzles which cause a liquid coolant to impinge, under pressure, on the floor of the base plate.

Abstract: A telecommunication system performs multihop TASI over every hop with a single instance of speech activity detection for each voice call. The system utilizes a Time-Space-Time circuit switch interposed between an input and an output trunk. The input time stage is configured to collect call samples from the input trunk and to map the physical slots associated with the samples to the switch slots of the conventional space switch portion of the circuit switch portion of the circuit switch. In-b signalling of the active state of a switch slot is provided by the input time stage to the output time stage via the space switch. The output time stage is configured to assign physical slots on the outgoing trunk to active switch slots and to discard inactive switch slots.

Abstract: A CMOS integrated circuit for driving capacitance devices is provided. The circuit has an input node and an output node and includes a first transistor operatively connected to the input node which is turned "on" and "off" by the input node to supply an output signal to the output node when turned "on". A second transistor is provided, the output of which is connected to the output node when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor prior to the second transistor, and to turn on the second transistor if and only if the slew rate of the output signal of the first transistor is less or slower than a given value.

Abstract: A computer system has a system memory, a central processing unit, an input/output controller, and at least one device. When the central processing unit wants data transferred to/from system memory from/to the device, it sends Indirect DAta Address Word (IDAW) commands to the I/O controller. Instead of performing a direct memory access (DMA) operation for each IDAW command, the I/O controller starts an IDAW look ahead procedure. In this procedure, the I/O controller checks to see if the system addresses of the system memory specified in the IDAW commands are contiguous. If so, the procedure combines IDAWs that specify contiguous system addresses up to the maximum DMA transfer length. Using this procedure, the number of DMA operations sent to the system memory is minimized, and the computer system has more efficient data transfer operations.

Abstract: An improved thin film magnetoresistive (MR) sensor uses an alloy comprising Fe.sub.(1-x) Mn.sub.x, where x is within the range of 0.3 to 0.4, as an antiferromagnetic layer to provide longitudinal exchange bias in the ferromagnetic MR layer. In a specific embodiment the exchange bias is at a high level and is independent of thickness of the antiferromagnetic layer over a wide range.

Abstract: In a data processing system having a system bus for coupling I/O units to a system storage unit, there is provided a mechanism for supplying to the I/O units a line size signal representing the line size of the system storage unit. A further mechanism is located in at least one of the I/O units for responding to this line size signal for adjusting the data transfer size of the I/O unit to match the system storage unit line size.

Abstract: A practical mathematical algorithm is used to solve the so-called "File Assignment Problem" (FAP). The FAP is partitioned into two sequential optimization problems, called the macro model and the micro model. The macro model is solved by a Non-Linear Programming Model (NLPM) and a Queuing Network Model (QNM). The NLPM takes as input detailed information on the computer system configuration and performance characteristics down through the DASD level, and, using the QNM as its objective function evaluator, determines the "optimal" DASD relative access rates as output. The micro model is solved by a Binary Linear Programming Model (BLPM), although the QNM is also involved to help determine the BLPM stopping criteria. The input to the micro model consists basically of the output from the macro model, together with statistics on the access rates of the various files in the computer system. The output from the optimization is an "optimal" assignment of files to DASDs.

Abstract: A method of operating a delay circuit to impose a selected delay on an electronic signal the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.

Abstract: An apparatus for removing heat from a heat generating device. The apparatus includes at least one heat conductive finned thermal device insert including a base having at least one first fin, and preferably haing a plurality of first fins, on a first surface and a second surface which is flat and a heat conductive second thermal device, preferably a cooling hat, having a plurality of second fins. The first fins are interspersed with the second fins. At least one of the first and second fins is of a thermally conductive, flexible material so that a gap otherwise existing between the interspersed fins is substantially eliminated. Finally, at least a portion of the first and second fins are biased against one another.

Abstract: An I/O bus expansion interface is disclosed which enables an I/O device having an n-bit data bus to be interfaced to an m times n-bit I/O data bus of a host processor. This I/O bus expansion circuit maximizes the computer processor's performance by providing full I/O data bus bandwidth and allowing overlap of processor execution and I/O bus expansion interface circuit operation. This is accomplished by: (1) prefetching multiple control and/or data fields from the I/O device and presenting that information to the host without delay and (2) burst writing multiple fields from the host to the bus expansion interface circuit, without delay of the host, and thereafter making these fields individually available to the I/O device.

Abstract: Disclosed is a memory access control device for a memory organized in 2.sup.n byte words and having the capability of addressing each byte in a word under control of byte select signals (BS), through an m-byte wide bus 22, with 2.sup.n /m being an integer k, to write or read data byte bursts comprising a variable count of bytes. For writing, k sets of m bytes received from bus 22 are stored into 2.sup.n registers 40 during each bus period T; they are then transferred into buffer 30 which comprises successive location of 2.sup.n bytes positions, through an alignment and control logic 42, which causes the buffer to be written in such a way that it maps the data arrangement in memory. This depends upon the least significant bits of the memory starting address determining the byte location within the memory words. Once the complete data burst is written into the buffer, the buffer content is transferred to the memory.

Abstract: The typewriter is equipped with the capability to check or verify the spelling of words as they are typed and the typewriter may also upon request from the operator provide candidate words from which the operator may select a word to replace a misspelled word. When a candidate word is selected, the typewriter electronic controls check the spelling of the misspelled word and delimit the zone which contains the erroneous characters. Only the characters that are within this bounded zone are erased from the page and the character which fit within the zone in the new or correctly spelled word are printed, eliminating the need to remove characters which are outside the zone and which are correct in the original word and will be correct in their position in the correctly spelled word.

Abstract: A method of continuously regenerating a metal containing acid solution enhanced with a salt-free material. The metal dissolved in a bulk metal containing acid solution is continuously oxidized by introducing a gas into a packed reaction vessel. The packed reaction vessel is in operative relationship with the bulk acid solution for recirculating regenerated solution and for receiving spent solution. The gas is introduced substantially cocurrently with the spent acid solution.

Abstract: In a circuit card assembly for use within an information processor (computer) wherein the assembly includes a fiber optic connector assembly as part thereof, there is provided means for enabling electrical connections to be made to the circuit card's circuitry in the same area as the fiber optic connector's housing so that charging of the card (to the potential of the mother board to which it will be coupled) can occur prior to coupling of the card to the board. Once the card is positioned and thus connected to the board, the charging means of the invention can be removed and a desired fiber optic connector inserted within the housing so that desired optical connections can be made with corresponding components (e.g., receiver, transmitter) which form part of the circuit card assembly. Both optical and electrical connections thus occur within the same housing.

Abstract: A connector system for a computer assembly is provided where the assembly includes a plurality of self-standing system frames with high density circuitry on support boards slidably mounted to the frames with the connectors facing a common face of the frames. The cabling between frames is provided by a self-standing cabling frame having connectors thereon arranged to correspond to the connectors on the plurality of systems frames and having alignment elements to align and fix the system frames and the cabling frames to provide simultaneous interconnection of the frames.

Abstract: A developer apparatus (29) for use in an electrostatic reproduction apparatus includes a large reservoir of toner (34, 44). The toner is located in a supply chamber (39) and is metered to a developer roller chamber (35) from which it is carried by a developer roller (31) past a doctor blade (36) to a photoconductor drum (19) for image development. A toner metering roller (41) rotates with the developer roller (31) to provide a continuous supply of toner from the supply chamber (39) to the developer chamber (35). Once an equilibrium level (65) is reached, the toner metering roller (41) acts to remove toner (34) from the developer chamber (35) to the supply chamber (39) to insure proper operation of the developer roller (31).

Abstract: A high performance, low power analog to digital converter is designed in BIFET technology utilizing the high gain, high performance of a bipolar comparator and the low power of a CMOS latch and CMOS encoding logic circuits. Using a FET dynamic latch, metastability is avoided, significantly reducing soft error rate.

Abstract: A thermoelectrically cooled integrated circuit package is provided which includes a thermally conductive dielectric substrate, an input connecting portion and an output connecting portion supported by the dielectric substrate, and an integrated circuit chip including an input terminal and output terminal. The input terminal is electrically connected to the input connecting portion via a first conductive material, and the output terminal is electrically connected to the output connecting portion via a second conductive material. The first conductive material and the second conductive material thermoelectrically cool the integrated circuit chip when a signal passes through the first conductive material and the second conductive material.

Abstract: A method for clipping two and three dimensional graphic primitives for use in a computer graphics workstation. During the first clipping stage, the system removes all graphic primitives which lie outside an arbitrary clipping volume or window that is an enlargement of the desired viewing volume or window. This clipping volume (window) is then projected and mapped onto a virtual viewport which is larger than the real viewport. After this mapping occurs, rendering effects (such as line styles, line width, pattern fill, hatch fill, etc.) are applied to the primitive. A subsequent stage of clipping is then applied to clip the virtual viewport to the real viewport which is the user's visible area. Use of the clipping volume (window) during the first stage of clipping makes it simpler to transform geometric primitives which are partially visible to the viewer, and gives visible primitives a richer set of invariant geometric properties so that their rendering effects may be more easily and correctly carried out.

Abstract: A push-pull driver circuit is disclosed comprising two stages. The first stage includes a current switch producing a dual phase output. The second stage includes a first emitter follower for output pull-up and a second emitter follower and a current mirror for output pull-down. The inputs of the first and second emitter followers are connected to respective output phases of the first stage. The outputs of the emitter followers are connected to respective terminals of the current mirror. The output of the second emitter follower also is connected to the output line being driven. A fixed biasing source maintains the current mirror transistors in conductive states at all times. Schottky diodes are connected to the current mirror transistors to prevent saturation.

Abstract: In a disk drive device having multiple disks on a spindle, one of the disks is written with a servo pattern prior to assembly of the servo disk with blank disks into the disk enclosure. The servo pattern consists of a first pattern arranged on each track center along one radial direction of the disk, and a second pattern arranged along the radial direction at each position corresponding to the position of each sector. Servo patterns on each of the disks, including the original servo disk are then written on each of the disks based on the original servo disk. If the disks, when assembled exhibit eccentricity, the second pattern will still be detected, permitting servo writing without complex equipment.

Abstract: Low melting temperature copper-containing solders are disclosed for soldering and rework on copper surfaces. The amount of copper required in the solder in order to inhibit dissolution of the copper surface to be soldered has been found to be dopant level, below the binary tin-copper eutectic point.

Abstract: Solder flux compositions and pastes made therefrom, consisting essentially of solder metal powder, an amount of non-corrosive water soluble flux, said water soluble flux comprising a mixture of 2 non-corrosive water-soluble components, one of which is a non-halogenated amine, preferably triethanolamine and the other of which is an organic moiety with a polar group, preferably GAFAC RE-610.

Abstract: In an electrophotographic reproduction device, such as a copier or a printer, having a transfer station (17) whereat toner images are sequentially transferred from the surface of a moving photoconductor (10) to the adjacent surface of sheets of moving and spaced transfer material, such as paper, the transfer station is controlled in a manner to produce a substantially similar electrical effect on the photoconductor both when a sheet of transfer material resides in the transfer station intermediate the photoconductor and the transfer station, and when no sheet of transfer material is intermediate the photoconductor and the transfer station.

Abstract: A timer including a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.

Abstract: A magnetic head/support assembly 10 for assembly into the data access mechanism 70 of a magnetic disk file comprises a magnetic head element 12 and a support structure 11, 20, 21 for the head element. The head/support assembly also comprises a head lead locator 27 including a frame 51 for locating and terminating the leads 15 from the head element 12 remotely from the element. The locator is attached to the support structure and the leads extend across the frame and are retained in fixed spaced apart relationship over a sufficient portion of their lengths to permit direct electrical connection to a correspondingly spaced pattern of conductors on external data channel circuitry carried by the access mechanism.

Abstract: Unique structured fields for delimiting the beginning and end of a data file sent to a print server in a computer network having a mixture of host processors and microprocessors for generating files to be printed. Each file sent to the print server is preceded by a unique beginning of file structured field and is terminated with a unique ending of file structured field.

Abstract: This invention speeds up the execution of instructions in an information processing system by tightly coupling two or more processors to a random access storage mechanism in such a manner that no arbitration is required and no processor is forced to wait while another processor accesses the storage mechanism. This is accomplished by coupling the processors to the storage mechanism in a time multiplexed manner which enables each processor to have a periodic regularly occurring turn at accessing the storage mechanism.

Abstract: Disclosed is a method of compressing a sequence of data symbols. The method includes the steps of sequentially appending symbols to a working substring to find the longest string that is duplicated in a history buffer or a lexicon. If the string is duplicated in the history buffer, then a history reference is emitted. If the string is duplicated in the lexicon, then a lexicon reference is emitted. If the string is not duplicated in either the history buffer or the lexicon, then a literal reference is emitted. The history buffer is a record of uncompressed data that has most recently been processed. The lexicon is a record of strings that has been emitted by means of history references.

Abstract: A neural network utilizing the threshold characteristics of a semiconductor device as the various memory elements of the network. Each memory element comprises a complementary pair of MOSFETs in which the threshold voltage is adjusted as a function of the input voltage to the element. The network is able to learn by example using a local learning algorithm. The network includes a series of output amplifiers in which the output is provided by the sum of the outputs of a series of learning elements coupled to the amplifier. The output of each learning element is the difference between the input signal to each learning element and an individual learning threshold at each input. The learning is accomplished by charge trapping in the insulator of each individual input MOSFET pair. The thresholds of each transistor automatically adjust to both the input and output voltages to learn the desired state.

Abstract: An integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer, further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.

Abstract: A line-adapter of a communications controller includes, for scanning the teleprocessing lines connected to it, cyclic scanning means FES exchanging information with the lines through a serial bidirectional link on which data and control informations are partitioned into frames and slots. Since both the FES and the serial link work with their own timings, an interface FESA is provided to adapt the FES scanning to the serial link structure. This FESA includes temporary storage means for storing on the one hand, data and control information transmitted from the LICs to the FES (10) through the inbound serial link, and on the other hand, data and control information transmitted from the FES to the LICs through the outbound serial link. The access of the FES, the outbound and inbound serial link to the storage means is time-shared and granted by an arbitration logic, according to the relative priorities of operation of said elements within the line-adapter of the communications controller.

Abstract: This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit or column lines are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines associated with a common sense amplifier. One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

Abstract: Disclosed is a method of decoding a stream of compressed data made up of a sequence of literal references, history references, and lexicon references. If the first bit of the stream is a zero, then the first reference is of the type literal and the first bit is followed by the 8-bit literal symbol itself. If the first bit is a one, then the first reference is either a history reference or a lexicon reference. If the second bit is a zero, then the first reference is of the type history and the second bit is followed by an offset value and a length value. If the second bit is a one, then the first reference is of the type lexicon and the second bit is followed by an index value. After the character of the first reference has been determined, the process is repeated starting with the first bit following the first reference.

Abstract: A lapping machine control system which utilizes a electromechanical probe to generate a signal responsive to the separation of the laps, which also represents the thickness of the part being lapped. The separation signal, which is unsuitable for direct control since it is too noisy, is used with a best fit algorithm to estimate the time to reduce the part to the desired thickness, based on the rate of material removal provided by extrapolated line representing the best fit of the lap separation signal. The machining is terminated when the extrapolated line reaches the intercept of time and thickness.

Abstract: According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a conventional way with the feedback loop connected to said output node (14). The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in a push pull configuration is reinforced to full swing (GND to VH) by the latch at the end of each transition. The state of the output node if forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15).

Abstract: A data processing system has files stored on disks in a tree structure of directories and files. The system is operated to rapidly open files which have been recently opened or for which partial path information is available, by accessing a drive cache in main memory. The cache has entries chained in a tree structure which is then searched to provide the same information during the opening process as that information which would otherwise have to be gotten from a disk. When the cache is full, a new entry replaces the least recently used entry.

Abstract: A circuit for limiting the effect of overshoot in a transformer of the type having a primary winding and a secondary winding. The secondary winding is coupled to a load and the circuit has an output. An auxiliary or ballistic winding is operatively connected to the transformer and is adapted to generate a winding voltage which varies in response to a voltage generated across the primary winding. An electronic switch, preferably a transistor, is interposed between the ballistic winding and the output of the circuit. The switch is capable of being disposed in a first position or a second position. In one preferred embodiment, the winding voltage is communicated to the circuit output when the switch is in the first position. An actuating arrangement is coupled with both of the ballistic winding and the electronic switch. The electronic switch is disposed into the first position by the actuating arrangement a predetermined time interval after the winding voltage has exceeded a predetermined reference voltage.

Abstract: Method for determining the baud rate of a data stream by comparison of captured data to known autobaud characters. Samples are received from the communication device and stored in memory until a set of the samples are accumulated. Then, a sample clock is divided in half and the odd numbered samples are compared to a set of known autobaud characters. If a match occurs, then the sample clock is assumed to be correctly synchronized with the incoming serial data stream. If a match does not occur, then the even samples are recirculated and eight more samples are collected. The sample clock is again divided in half and the odd numbered samples are compared to the set of known autobaud characters. If a match occurs, then the sample clock is assumed to be correctly synchronized with the incoming data stream. These steps are repeated until an autobaud character match is found or an error situation is determined.