Abstract: a system of arbitration for access to a common memory by two asynchronous microprocessors without excluding either microprocessor for more than a predetermined, limited period of time. Two asynchronous microprocessors are connected to a common memory through an arbitration controller with a connection to transmit a "not ready" signal to one microprocessor requesting access when the other is in the process of accessing the common memory. A flip flop is connected to generate a predetermined signal output when a microprocessor requires access to the common memory, and this predetermined signal initiates a shift register to provide the internal timing of the asynchronous microprocessor requiring such access to bring it into synchronism with the clock controlling the internal cycle of the common memory.

Abstract: A data processing system having a dual arbiter for controlling access to a system bus where two processors, each clocked by one of two timing signals having equal periods but out of phase by half a period, operate synchronously each to the other, but outphased by the half period of the clock signal, and generate equal priority signals requesting access to a system bus, each processor in a time distinct and non overlapped phase of the respective timing signals, and where an arbitration unit grants system bus access to either one or the other requesting processor on the time order in which the access requesting signals are received, the granting being performed asynchronously and without sampling and set up delays.