Abstract: A power factor correction circuit in which an inductor current is detected separately as a charging current indication signal and a discharging current indication signal by using a current sense resistor and a current sense circuit. A scaled-down output DC voltage is compared with a predetermined reference DC voltage by using an error amplifier which serves to produce an output voltage error signal. The output voltage error signal is then multiplied with a divided-down rectified input line voltage through the use of the multiplier to generate a sinusoidal reference signal. The sinusoidal reference signal is used by peak and valley comparators which also receive the charging and the discharging current indication signals. The outputs from the peak and the valley comparators are used to control a FET transistor which controls the input line current. As a result, the power factor correction circuit is capable of effectively eliminating a dead time and thereby achieving a near unity power factor.

Abstract: An overvoltage protection circuit for a CMOS electronic multimeter circuit uses a pair of complementary field-effect protection transistors connected to each input line of the meter circuit. The gate electrodes of the protection transistors are connected to bias voltage sources which provide bias voltages with magnitudes slightly less than the meter power supply voltages. The protection transistors go into conduction when an overvoltage condition causes the voltage on the input to exceed the bias voltages and the conducting protection transistors clamp the input voltage to substantially the bias voltage. Current caused by an overvoltage condition is shunted to ground thereby avoiding a charging condition in the power supplies.

Abstract: An electronic motor protection system is shown having a power supply usable with multivoltage supplies and providing protection from over-temperature conditions caused by various fault conditions. The system also has optional features of a time delay for re-energization and for low voltage protection. The system is mounted on a circuit board and encased in potting material which also locks the two housing parts together. A miswiring feature is also provided to prevent connecting line voltage to the control circuit or sensor terminals.

Abstract: A phase sequence protection circuit is shown in which first and second resistors (R1, R2) and a first capacitor (C1) all having equivalent impedance are connected in a Y configuration and coupled to power source leads (A, C, B) of a three phase power supply, resistor R1 being coupled to phase A, capacitor C1 to phase B and resistor R2 to phase C. A comparator network (12) is connected in line with the first resistor (R1) and, in one embodiment will cause a solid state switch (Q1) to conduct when the phases are out of sequence. In a second embodiment a buffer portion (COMP2) is provided to add switching hysteresis which also reverses the switching logic causing the solid state switch (Q1) to conduct when the phases are in sequence. In another embodiment the comparator network (12") is provided with the buffer portion (COMP2) for switching hysteresis and arranged to cause the solid state switch (Q1) to conduct when the phases are out of sequence.

Abstract: An anti-theft starter circuit system and electronic circuit security module housing apparatus for use therewith in a motor vehicle having an electrically operable starter motor and solenoid arrangement, the electronic circuit security module housing being mechanically adaptable to and installed directly upon existing starter solenoids, and a system access code entry device within the vehicle operator's compartment.

Abstract: A magnetic coil assembly with a connector arrangement which prevents explosion or other accident due to the mismatch of voltage rating between a surge absorber and a magnetic coil, allows only the surge absorber to be changed easily if it has been damaged, and ensures ease of automatically assembling the surge absorber into the magnetic coil assembly. The magnetic coil assembly includes a coil spool, a winding wound around the coil spool, and coil terminals mounted on the coil spool and electrically connected with the winding. The surge absorber is connected mechanically and removably with the coil spool or coil terminals, using connectors that may uniquely relate to the ratings of the absorber and coil, and the absorber terminals of the surge absorber are brought into contact with, and therefore are electrically connected with, the coil terminals.

Abstract: A high voltage substation level surge suppression system is disclosed comprising three primary elements. Two surge arrestors are used, separated by a surge interceptor. The first surge arrestor encountered is a high energy dissipater. It conducts most of the energy from a lightning induced or other fast rising high voltage surge to ground. The surge interceptor, comprises an inductor formed by wrapping insulated wire around a tube through which is inserted a parallel high energy resistor. The inductor element in the Surge Interceptor operates to delay the fast rise surge or transient long enough that the high energy dissipater can operate. The resistor element operates to dampen ringing or oscillations caused by the interaction between the inductor and a high voltage lightning strike and to dissipate some of that energy. Finally, the second arrestor, the voltage controller, operates to clamp the voltage after the Surge Interceptor to a set level.

Abstract: A power supply is provided for a presentation system having a light source which allows for overdriving of the light source, but protects against transient surges on the input line when overdriving the light source. The power supply includes an input line connected to the external ac source, two output lines, and a relay selectively connecting the input line to one of the two output lines. The relay is indirectly controlled by a voltage sense circuit which converts the ac source voltage to a dc output voltage. The dc output voltage is examined to determine whether the input line is in a low- or high-voltage state, the high-voltage state corresponding to a surge on the line.

Abstract: An electrostatic discharge (ESD) protection circuit for integrated circuitry having a switching ground bus for isolating switching noise includes an ESD protection bus. A first transistor pair includes a PNP transistor and an NPN transistor, with each of the transistors having an emitter connected to a signal input/output pad. A second transistor pair has a PNP transistor and an NPN transistor having emitters connected to the switching ground bus. For each of the PNP transistors, the base is connected to the ESD protection bus and the collector is connected to a "clean" ground bus. For each of the NPN transistors, a base is connected to the clean ground bus and a collector is connected to the ESD protection bus. In this configuration, the PNP of one transistor pair and the NPN of the other transistor pair are able to operate as a distributed silicon controlled rectifier to protect a drive transistor during an ESD event. Optionally, a switching V.sub.

Abstract: A fault current protection system for a traction vehicle propulsion system including a synchronous generator having armature and field windings and power conditioning circuitry connecting the generator armature windings to a traction motor employs a normally charged capacitor which, in response to a fault signal resulting from excess current in the generator armature windings, is electrically switched into parallel with the excitation current source connected to the generator field windings so as to discharge through the generator field windings and commutate the excitation current source.

Abstract: A modulating system for converting data of a basic data length of m bits into a variable length code (d, k; m, n; r) of a basic code length of n bits, which comprises the steps of: judging a binding length i (i=1.about.r) of the basic data; uniformly converting data of m.times.i bits into a code of n.times.r bits by using a conversion table for converting data of m.times.r bits where the binding length i is the maximum binding length r, and including at least one conversion table where the binding length i is less than r; and taking out specific bits from the code of n.times.r bits thus obtained on the basis of the judged binding length i to output them as a modulation code.

Abstract: In an electronic IC package, an I/O PAD circuit design which protects 3 Volt optimized I/O functional circuits from damage due to the application of external 5 Volt signals to the I/O PAD both while the functional circuit design is powered on and powered off. When the I/O circuits associated with the I/O PAD are powered on, the present invention protects the I/O circuits by applying well known designs. However, when the I/O circuits associated with the I/O PAD are powered off, the present invention draws power from the external 5 Volt signal to activate additional transistors to protect the powered off I/O circuits.

Abstract: A shorted diode protection system for a traction vehicle propulsion system including a synchronous generator having armature and field windings and a bridge rectifier circuit coupling the generator armature windings to a traction motor employs a normally non-conducting solid-state controllable electric valve in parallel with the generator field windings. When a rectifier diode of the bridge rectifier circuit fails short, an a-c current is reflected into the generator field winding circuit. Upon detection of this reflected current, the valve is switched into a conducting state, thereby limiting the voltage on the generator field windings.

Abstract: In a circuit configuration for the shutoff of a semiconductor component in the event of excess current, the semiconductor component has gate and cathode terminals and is controlled by the field effect. A controllable switch is connected between the gate and cathode terminals and is made conducting by a control signal. A device controls the controllable switch to a range of high on-state DC resistance when there is excess current and a shutoff signal is simultaneously present.

Abstract: The invention relates to a surge arrester arrangement comprising a surge arrester with a number of ZnO blocks arranged between two end electrodes as well as a cut-out device arranged in series with the arrester for automatically disconnecting the arrester in the event of arrester failure. The central part in the cut-out device is a ZnO block (1) with a higher relative energy capability than the blocks in the arrester. In this way, the block in the cut-out device can only break if the arrester connected in series with the device has failed, whereby incorrect tripping of the device is prevented.

Abstract: A surge absorbing device with protection function to protect a circuit from overvoltage and overcurrent, comprising a gap or microgap surge absorbing element and a lower melting point metal wire connected therewith. A plurality of gap or microgap surge absorbing elements to the circuit to be protected, and each of the lower melting point metal wires respectively corresponding to each of gap or microgap surge absorbing elements being in contact with all of the gap or microgap surge absorbing elements.

Abstract: A modem located on a PC card. An I/O socket is mounted on one end of the PC card and sideswipe contacts are positioned long e one or more sides. The I/O socket has a plurality of positions including one or more positions which are electrically connected to the modem. A relay is located in the PC card, and has one side connected in common to the modem and the positions on the I/O socket. The other side of the relay is connected to the sideswipe connectors. The control input to the relay is connected to a position of the I/O socket separate from the modem positions. A voltage source is connected to a position in the socket separate from the modem positions and the control signal position. An I/O plug is designed to have one side connected to the telephone network and the other side connected to the I/O socket such that all pins in the plug mate with the corresponding positions in the I/O socket.

Abstract: The present invention is directed to effectively prevent "load short-circuit breakdown" of a power Darlington transistor. When a potential different between a base BX and emitter E at a final stage of a power Darlington transistor (20) is at a specified level of voltage determined by base-emitter forward voltage of a protective bipolar transistor (32), the protective bipolar transistor (32) turns on, and accordingly, base current I.sub.B at an initial stage of the power Darlington transistor (20) is bypassed to the emitter E at the final stage. Hence, excessive rising of collector current I.sub.C of the Darlington transistor (20) is suppressed, and "load short-circuit breakdown" is prevented.

Abstract: A surge arrester assembly includes an electrically conductive container having disposed therein a surge arrester and a meltable element. The surge arrester has a first electrode in electrical contact with the container and a second electrode not in electrical contact with the container. The meltable element is an electrically conductive element in thermal contact with the surge arrester. The meltable element is located and configured so as to melt in response to a selectable level of thermal energy generated by the surge arrester, in such a manner as to create an electrical short circuit between the first electrode and the second electrode.

Abstract: An enhanced bipolar-transistor apparatus for protecting electronic devices from electrostatic discharge damage. The apparatus is built around a bipolar transistor coupled between a power rail and the circuit to be protected. The protection is based on the high-current-capacity path through the bipolar transistor which is opened up either by collector-to-emitter punch-through in the bipolar transistor or by the bipolar transistor going into normal conduction upon being turned on by a switch coupled to the base of the bipolar transistor. In the preferred embodiment the switch is a MOS transistor that is designed to undergo source-to-drain breakdown at a fixed threshold voltage, whereupon it activates the bipolar transistor which in turn discharges the overvoltage.