Patents Examined by A. Decady
  • Patent number: 6938195
    Abstract: A communication terminal apparatus returns a unit of transmission with an error detected. A base station apparatus generates information indicating a position of an error within the unit of transmission while comparing a unit of transmission returned from the communication terminal apparatus with a corresponding unit of transmission stored in a buffer previous to transmission of the unit of transmission. The base station apparatus transmits the generated information to the communication terminal apparatus. The communication terminal apparatus corrects the error of the unit of transmission on the basis of the information.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: August 30, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Guizeng Shi, Osamu Kato, Mitsuru Uesugi
  • Patent number: 6851079
    Abstract: A circuit that may be used to implement boundary scan testing. The circuit generally comprises a pad circuit, a core logic, a cell, and a test circuit. The pad circuit may be configured to transfer a data signal in response to a pad control signal. The core logic may be configured to (i) exchange the data signal with the pad circuit and (ii) present a control signal. The cell may be configured to (i) transfer the data signal between the pad circuit and the core logic and (ii) swap the data signal and a test signal. The test circuit may-be configured to (i) exchange the test data signal with the cell, (ii) store a test control signal, and (iii) multiplex the test control signal and the control signal to present the pad control signal.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: February 1, 2005
    Assignee: LSI Logic Corporation
    Inventor: Michael A. Hergott