Abstract: A single instruction, multiple data stream parallel computer using bit-serial arithmetic whereby the machine's basic operation is performing Boolean operations on huge vectors of 0's and 1's. The machine utilizes an architectural approach whereby the memory of a conventional machine having 2.sup.k words each t bits long, is reorganized into p registers each 2.sup.k bits in length and adding processor logic to each bit position of the registers and a communication network being added which allows for the 2.sup.k pieces of processing logic to interact. This machine is capable of executing a wide variety of algorithms at a speed of 2.sup.k /p to 2.sup.k /p.sup.2 faster than conventional machines. The machine provides for an ability to handle a variety of algorithms by interconnecting the individual processor elements in a general interconnection network capable of performing a permutation of n bits held one in every processor element in a time of (O(log(n)).

Abstract: An input device, for enabling a first word represented in a first language is adapted for an electronic translator for obtaining a second word represented in a second language, equivalent to the first word, in response to the input of the first word. The input device includes a specifying circuit for specifying a letter, an input circuit for controlling the specifying circuit to input the letter into the electronic translator to at least partially define the first word, a memory for memorizing a plurality of words containing the first letter, an access circuit provided for addressing the memory to retrieve the words, and a display responsive to the access circuit for displaying the words. The access circuit is operated in response to the operation of the input circuit so that the memory develops words starting with the input letter.

Abstract: A video display control circuit, for an intelligent terminal, includes a large cost efficient Random-Access Memory (RAM). A portion of the RAM memory is utilized as a high speed character generator instead of employing a dedicated Read Only Memory (ROM). Novel timing and memory control circuits are provided which permit characters to be generated witout any delay or change of real character timing. The characters in RAM may be modified or changed which is not possible with dedicated Read Only Memories.

Abstract: A logic network and method for processing columns of vertically oriented imaging data bits to produce control signals for operating a linearly slanted print head, includes writing different equal byte segments of each such column into a RAM memory while pre-skewing successive bytes, respectively, from one another by the equivalent of the number of columns of print resolution capability between successive print elements of the print head represented by each byte. Thereafter, skewing of the imaging data bits is completed during readout from memory, by fetching in columnar order the bits required for operating the print elements to print the image data under the print head during a given print cycle.

Abstract: An electronic dictionary and language interpreter includes an input keyboard actuated for entering a pair of a new word or words and a translated word or words corresponding thereto, a read/write memory for memorizing the pair of the word or words and the translated word or words, a read-only memory fixedly containing a plurality of pairs of a word/words and a translated word/words, and an access circuit operated for addressing the read/write memory and the read-only memory to cause retrieval of any desired pair of a word and a translation word or words among the new word or words and the translated word or words, and the plurality of pairs of the word/words and the translated word/words. Preferably, there is further provided a word cancellation circuit useful in permitting the removal of the pair of the new word or words and the translated word or words from the read/write memory.

Abstract: In a data processing system, a bus is provided for the transfer of information between units coupled to the bus. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Priority is normally granted on the basis of physical position on the bus, highest priority being given to the first unit on the bus and lowest priority being given to the last unit on the bus. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively, only one such unit being capable of having the grant of a bus cycle at any given time, whereas any number of such units may have its request pending at any particular time.

Abstract: Each section includes a data processing unit (1) provided with circuitry (7) for transmitting processed data to the other station, as well as circuitry (7) and (2) for reception of the data processed by the other station. The transmission occurs between the stations via only one connection 1.sub.3, plus a return connection such as 1.sub.1.

Abstract: This apparatus controls the execution and content of computer programs in equipment containing a computer by causing the transfer of program data elements, including computer instructions, with a memory of the apparatus. The selection of data for transfer is effected either by the computer, operating in a normal manner, or by the apparatus, which may shift data selection between these two selection options so that the computer ceases selection of data constituting one program and begins selecting data of another program. While data elements are being transferred with the computer, other elements of the memory are available for examination and modification such that new programs, the content of which may depend on the results of prior program execution, can be loaded, executed, and examined without interrupting, delaying, halting, or otherwise disturbing the instruction flow of the computer equipment.

Abstract: An apparatus for monitoring automatically plural sheets of printed papers, includes a plurality of photosensors placed across the printed papers' moving direction for scanning and detecting a printed surface of each printed paper to produce analog signals designating dark levels of the printed surface thereof when each of the printed papers is being transferred, an AD converter for converting the analog signals into digital signals at a plurality of sampling points, a standard memory for storing such digital signals, a plurality of monitoring memories for storing such digital signals, circuitry for comparing the digital signals of the standard memory with the digital signals of the monitoring memories at the corresponding sampling points to decide whether or not the digital signals of the monitoring memories are within a tolerance range of the digital signals of the standard memory so that either "NO" signals or "YES" signals are produced, circuitry for counting only such "NO" signals to produce an "irregular

Abstract: A control circuit is used for matrix drive recording. It includes a microprocessor, a RAM for storing data to be recorded therein, an address signal editing circuit for modifying the input addresses to the RAM, a shift register for converting the data from parallel to serial form and transferring it to a recording circuit, and a DMA controller for reading the data from the RAM and transferring it to the shift register.

Abstract: An electronic translator includes a memory for storing a plurality of words. The memory is characterized in that it stores the plurality of words in random order with an address code representing an address of the memory added to each of the words. The address denoted by the address code added to each of the words is the address of the next word in alphabetical sequence whereby the randomly words may be addressed in the alphabetical order.

Abstract: A merging device is used for combining a first list and a second list in order to form a result list. All lists satisfy a linear ordering criterion. At the beginning of the actual merging operation, the second list is stored in a random access memory. This memory is divided into (kmax) memory blocks, the second list filling at the most the (kmax-2) non-largest memory blocks thereof. Efficient bookkeeping is achieved by means of two block list updating devices.

Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor.

Abstract: In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory is governed by the age since first write. The host processor passes an AGEOLD parameter to the memory subsystem and this parameter regulates the trickling of segments. Unless the memory system is idle (no I/O activity), no trickling takes place until the age of the oldest written-to segment is at least as great as AGEOLD. A command is generated for each segment to be trickled and the priority of execution assigned to such commands is variable and determined by the relationship of AGEOLD to the oldest age since first write of any of the segments. If the subsystem receives no command from the host processor for a predetermined interval, AGEOLD is ignored and any written-to segment becomes a candidate for trickling.

Abstract: In a data processing system including a processor, a bulk memory, a cache, and a storage control unit for controlling the transfer of data between the bulk memory and the cache, a timestamp is generated with each write command. A linked list is maintained, having an entry therein corresponding to each segment in the cache which has been written to since it was moved from the bulk memory to the cache. The timestamp accompanying a write command which is the first command to write to a segment after that segment is moved from bulk memory to the cache is entered into the list at the most recently used position. An entry in the linked list is removed from the list when the segment corresponding thereto is transferred from the cache to the bulk memory. The linked list is utilized to update a value TOLDEST, which represents the age of the oldest written-to segment in the cache that has not been returned to bulk memory since it was first written to.

Abstract: A direct buffer access circuit provides a buffer memory for use with a host central processing unit and a peripheral controller for controlling an external data storage device such as a disk or tape drive. The buffer is connected so that both the host and the controller have direct access to the buffer. The host can thus transfer data to the buffer at its own data rate independently of the transfer rate of the controller. The buffer may include either a random access memory which is addressed by a counter, or a first-in/first-out memory. The buffer is controlled by signals received from either the host or the controller.

Abstract: In a cache memory unit including a cache directory identifying signal groups stored in an associated cache storage unit, apparatus and method are disclosed for searching the cache directory during a second portion of the cache memory cycle when the cache directory is not needed for normal operation, to determine if an invalid signal group is stored in the associated cache storage. When an invalid signal is found in the cache storage, this signal group is rendered unavailable to the data processing unit during the present cache memory cycle without interrupting the normal cache memory operation during succeeding cache memory cycles.

Abstract: A time delay memory system is used for enhancing the reliability of a data processing system or the like, wherein the critical information contents of temporary storage means are preserved from destruction by the adverse effects of an externally originated, transient condition. Critical information, which includes time-dependent critical data and a time reference, is periodically collected from a scratch pad memory and a timer respectively. The critical information is transferred to secondary storage means and remains there throughout a predetermined delay interval, substantially immune to the adverse effects of any transient condition. The delay interval exceeds the expected duration of the transient condition and its adverse effects. If the system is switched to a recovery mode by the occurrence of a transient condition, the critical data and the time reference are reloaded from the secondary storage means into the scratch pad memory and timer respectively at the end of the delay interval.

Abstract: A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing a user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object. The system also includes stacks for containing information relating to the current state of execution of the system.

Abstract: There is disclosed a data processing system comprising a plurality of processors having different processing speeds and connected with a synchronous common bus, the processors being able to access a common memory connected with the common bus.A high frequency master clock signal generating means is provided in common for the processors of the system and the respective processors can be operated with the associated different machine cycles determined in accordance with the corresponding different processing speeds by frequency-dividing the master clock signal. In addition, each processor can be operated with different machine cycles depending on its operations.