Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.

Abstract: A silicon carbide (SiC) Schottky diode comprises a layer of N-type SiC and a layer of P-type SiC in contact with the layer of N-type SiC creating a P-N junction. An anode is in contact with both the layer of N-type SiC and the layer of P-type SiC creating Schottky contacts between the anode and both the layer of N-type SiC and the layer of P-type SiC. An edge of the layer of P-type SiC is electrically active and comprises a tapered negative charge density at the P-N junction, which can be achieved by a tapered or sloping edge the layer of P-type SiC.

Abstract: A display device includes a substrate. A first electrode is disposed on the substrate. A pixel definition layer is disposed on the substrate. A second electrode is disposed on the first electrode and the pixel definition layer. An organic emission layer is disposed between the first electrode and the second electrode. A planarization layer is disposed on the second electrode. A low refractive index layer is disposed on the planarization layer and overlaps the pixel definition layer. A high refractive index layer is disposed on the planarization layer and overlaps the second electrode. The high refractive index layer has a higher refractive index than that of the low refractive index layer.

Abstract: Semiconductor wafers useful for NAND circuitry and having a front side, a rear side, a middle and a periphery, have an Nv region which extends from the middle to the periphery; a denuded zone which extends from the front side to a depth of not less than 20 ?m into the interior of the semiconductor wafer, where the density of vacancies in the denuded zone, determined by means of platinum diffusion and DLTS is not more than 1×1013 vacancies/cm3; a concentration of oxygen of not less than 4.5×1017 atoms/cm3 and not more than 5.5×1017 atoms/cm3; a region in the interior of the semiconductor wafer which adjoins the denuded zone and has nuclei which can be developed by means of a heat treatment into BMDs having a peak density of not less than 6.0×109/cm3, where the heat treatment comprises heating the semiconductor wafer to a temperature of 800° C. over a period of four hours and to a temperature of 1000° C. over a period of 16 hours. The wafers are produced by a unique RTA treatment of Nv wafers.

Abstract: A method for making a semiconductor device is disclosed. A substrate comprising semiconductor device elements is provided. A top conductive pad and an anti-reflective coating are patterned over the substrate. The anti-reflective coating is disposed on the top conductive pad. At least one passivation film is formed over the substrate and the anti-reflective coating. The at least one passivation film and the anti-reflective coating are etched to form a trench therein so as to expose a portion of the top conductive pad.

Abstract: A method is described for preparing a nanorods assembly. The method comprises providing a mixture comprising at least a liquid crystal and nanorods and depositing said mixture on the surface of at least substrate. The method further comprises aligning said nanorods with their long axis of the nanorods along a preferred direction on said substrate resulting in a nanorods and liquid crystal assembly, said aligning being performed by applying an external alternating current electrical field.

Abstract: A light-emitting element comprises a light-emitting semiconductor stack comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a reflective layer formed on the light-emitting semiconductor stack; a barrier layer formed on the reflective stack; a protection layer formed on the barrier layer, comprising a first through hole and a second through hole; a first height balancer filled in the first through hole and formed on the protection layer; a second height balancer filled in the second through hole and formed on the protection layer; and a conductive contact layer comprising a first conductive part formed on the first height balancer and a second conductive part formed on the second height balancer.

Abstract: A light emitting device according to an embodiment includes a body having a recess; a light emitting chip disposed in the recess; and a first dampproof layer sealing the light emitting chip and extended from a surface of the light emitting chip to a bottom of the recess, wherein the light emitting chip includes a wavelength range of 100 nm to 280 nm, and the first dampproof layer includes a fluororesin-based material.

Abstract: Devices and methods are provided to construct resistive random-access (RRAM) array structures which comprise RRAM memory cells, wherein each RRAM memory cell is formed of multiple parallel-connected RRAM devices to reduce the effects of resistive switching variability of the RRAM memory cells.

Abstract: A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.

Abstract: A method of manufacturing a semiconductor device includes replacing sacrificial layers with conductive patterns through slits and at least one opening that pass through a stack structure. The stack structure includes interlayer insulating layers and the sacrificial layers. The interlayer insulating layers and the sacrificial layers surround a support and are alternately stacked on each other.

Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.

Abstract: A substrate for semiconductor elements includes a terminal part including a first surface, a second surface opposite to the first surface, and side surfaces joining the first surface and the second surface, and a resin part covering the side surfaces and exposing the first surface of the terminal part. The resin part has a multi-layer structure including a first resin and a second resin, and the first resin is provided in contact with the side surfaces of the terminal part. The first resin and the second resin include a filler, and an amount of the filler included in the first resin is smaller than an amount of the filler included in the second resin.

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer and a trench isolation. The semiconductor substrate has a front side surface and a back side surface opposite to the front side surface. The radiation sensing member is disposed in a photosensitive region of the semiconductor substrate and extends from the front side surface of the semiconductor substrate. The radiation sensing member includes a semiconductor material with an optical band gap energy smaller than 1.77 eV. The device layer is over the front side surface of the semiconductor substrate and the radiation sensing member. The trench isolation is disposed in an isolation region of the semiconductor substrate and extends from the back side surface of the semiconductor substrate.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.

Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

Abstract: Provided is a method of manufacturing a bump structure, the method including a first step for preparing a wafer including a plurality of chips each including a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer, a second step for attaching a backgrinding film to an upper surface of the wafer, a third step for grinding a rear surface of the wafer by a certain thickness, a fourth step for forming a flexible material layer on a second rear surface of the wafer after being ground, and then attaching dicing tape including a ring frame, to the flexible material layer, a fifth step for removing the backgrinding film and then performing a curing process to harden the flexible material layer, and a sixth step for performing a dicing process to cut the plurality of chips into individual chips.