Patents Examined by A O Williams
  • Patent number: 11562977
    Abstract: A semiconductor device includes a substrate, a resin case, and a wiring member having an exposed portion adjacent to a first fixing portion fixed in a wall surface of the resin case and exposed to outside, and a second fixing portion fixed in the wall surface of the resin case at a position different from the first fixing portion with respect to a portion extending from the first fixing portion into the resin case, in which the wiring member is bonded to a surface of the semiconductor element by solder in the resin case, and has a plate shape having a length, a thickness, and a width, in which the wiring member has the thickness being uniform and is flat in the resin case, and the width of the second fixing portion is narrower than the width of the exposed portion.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: January 24, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Naoki Yoshimatsu
  • Patent number: 11545567
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: January 3, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Patent number: 11502059
    Abstract: A semiconductor package includes: a first thermal pillar disposed on a package substrate, and having an opening; a first chip stack disposed on the package substrate and in the opening of the first thermal pillar, and including a first lateral surface; a semiconductor chip disposed on the package substrate and in the opening, wherein the semiconductor chip is spaced apart from the first chip stack; and a first heat transfer film disposed between the first thermal pillar and the first lateral surface of the first chip stack.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heejung Hwang, Jae Choon Kim, Yun Seok Choi
  • Patent number: 11488892
    Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 1, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
  • Patent number: 11417624
    Abstract: An electronic device includes: a first resin layer having a first resin layer main surface and a first resin layer inner surface; a columnar conductor having a columnar conductor main surface and a columnar conductor inner surface and penetrating the first resin layer in direction z; a wiring layer connecting the first resin layer main surface and the first conductor main surface; an electronic component being electrically connected and joined to the wiring layer; a second resin layer having a second resin layer main surface facing the same direction as the first resin layer main surface and a second resin layer inner surface being in contact with the first resin layer main surface, covering the wiring layer and the electronic component; and an external electrode closer to the side where the first resin layer inner surface faces than the first resin layer and is electrically connected to the columnar conductor.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: August 16, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Hideaki Yanagida
  • Patent number: 11404337
    Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 2, 2022
    Assignee: Apple Inc.
    Inventors: Kunzhong Hu, Chonghua Zhong, Jiongxin Lu, Jun Zhai
  • Patent number: 11398423
    Abstract: A semiconductor assembly includes a carrier element with a first carrier element conductor path, a semiconductor chip, an electrically insulating element having a first insulating element conductor path, and a first spacer element. The semiconductor chip is connected electrically and mechanically on a first semiconductor side via a first connecting material to the first carrier element conductor path. The semiconductor chip is connected on a second semiconductor side, which faces away from the first semiconductor side of the semiconductor chip, via a second connecting material to the first insulating element conductor path, which is arranged on a first insulating element side of the electrically insulating element. The first spacer element is arranged for maintaining a distance between the carrier element and an assembly element facing toward the second semiconductor side of the semiconductor chip and is connected mechanically to both the carrier element and the assembly element.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: July 26, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ewgenij Ochs, Stefan Pfefferlein
  • Patent number: 11398437
    Abstract: A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 26, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Bongyong Lee, Bohee Kang, Doojin Choi, Kyeongseok Park, Thomas Neyer, Jeongwoo Yang
  • Patent number: 11374118
    Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 28, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
  • Patent number: 11348887
    Abstract: A radio-frequency module includes: a module substrate having first and second main surfaces; a semiconductor IC having third and fourth main surfaces and mounted on the first main surface with the third main surface between the module substrate and the fourth main surface; and first and second electrodes extending perpendicularly to the first main surface. The cross-sectional area of the second electrodes is smaller than the cross-sectional area of the first electrodes. The semiconductor IC viewed in plan has first and second sides parallel to each other and third and fourth sides parallel to each other. The first electrodes are distributed over a first region between the first side and a side facing the first side and a second region between the second side and a side facing the second side. The second electrodes are in a third region between the third side and a side facing the third side.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 31, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yusuke Naniwa, Hideki Muto
  • Patent number: 11348994
    Abstract: A fingerprint sensor includes: a base substrate including a plurality of pixel regions; a sensing dielectric structure formed on the base substrate in the pixel regions; and a sensing connection structure formed in the sensing dielectric structure. The sensing dielectric structure exposes the sensing connection structure and the sensing connection structure is connected to the base substrate. The fingerprint sensor further includes a plurality of electrode plates formed on surfaces of the sensing dielectric structure and the sensing connection structure. A plurality of protrusions are formed on surfaces of the electrode plates. The fingerprint sensor further includes an insulation medium structure formed on the plurality of electrode plates.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: May 31, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fu Gang Chen
  • Patent number: 11348865
    Abstract: A substrate for an electronic device may include one or more interconnect pockets. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees. Individual interconnects may be located within respective individual ones of the interconnect pockets.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Praneeth Akkinepally, Jieying Kong, Frank Truong
  • Patent number: 11342250
    Abstract: A lead frame for a hermetic RF chip package includes: a first capacitor unit formed of a conductive material in a rectangular shape having a width smaller than a length to receive an input of an RF signal applied to the package circuit; a first inductor unit connected to the first capacitor unit and formed of a conductive material in a rectangular shape having a width greater than a length; a second capacitor unit connected to the first inductor unit and formed of a conductive material in a rectangular shape having a width smaller than a length; and a second inductor unit connected to the second capacitor unit and formed of a conductive material in a rectangular shape having a width greater than a length to transfer an RF signal input through the first capacitor unit to the RF chip.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 24, 2022
    Assignee: WAVEPIA CO., LTD.
    Inventor: Sang-Hun Lee
  • Patent number: 11335556
    Abstract: Methods and materials for growing TMD materials on substrates and making semiconductor devices are described. Metal contacts may be created prior to conducting a deposition process such as chemical vapor deposition (CVD) to grow a TMD material, such that the metal contacts serve as the seed/catalyst for TMD material growth. A method of making a semiconductor device may include conducting a lift-off lithography process on a substrate to produce a substrate having metal contacts deposited thereon in lithographically defined areas, and then growing a TMD material on the substrate by a deposition process to make a semiconductor device. Further described are semiconductor devices having a substrate with metal contacts deposited thereon in lithographically defined areas, and a TMD material on the substrate, where the TMD material is a continuous, substantially uniform monolayer film between and on the metal contacts, where the metal contacts are chemically bonded to the TMD material.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 17, 2022
    Assignee: Ohio University
    Inventors: Eric Stinaff, Martin Kordesch, Sudiksha Khadka
  • Patent number: 11335671
    Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 17, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Zhixin Cui, Rajdeep Gautam
  • Patent number: 11322430
    Abstract: A semiconductor device and a semiconductor module which can be reduced in size while ensuing insulation are provided. In the semiconductor device, a lead frame on which a circuit pattern is formed is provided on an insulation substrate; the circuit pattern of the lead frame is joined to the back-side electrode of a semiconductor chip via a solder layer, and the lead frame is electrically connected with the top-side electrode of the semiconductor chip via a wire; the lead frame 1 includes a terminal inside a mold-sealing resin and a terminal exposed to a space outside the mold-sealing resin, and the terminal is connected to a terminal block via a solder layer; and the lead frame, the insulation substrate, the semiconductor chip and the terminal block are integrally molded and sealed by the mold-sealing resin.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 3, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hodaka Rokubuichi, Kuniyuki Sato, Kiyofumi Kitai, Yasuyuki Sanda
  • Patent number: 11316292
    Abstract: A semiconductor power module includes an electrically conductive carrier plate, a power semiconductor chip arranged on the carrier plate and electrically connected to the carrier plate, and a contact pin electrically connected to the carrier plate and forming an outer contact of the semiconductor power module. The contact pin is arranged above a soldering point. The soldering point is configured to mechanically directly or indirectly fix the contact pin on the carrier plate and to electrically connect the contact pin to the carrier plate. The contact pin is electrically connected to the carrier plate via a further connection. The further connection has a portion which is mechanically flexible in relation to the carrier plate.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies AG
    Inventors: Tomas Manuel Reiter, Mark Nils Muenzer, Marco Stallmeister
  • Patent number: 11289415
    Abstract: A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 ?m or less.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 29, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mizuho Ishikawa, Kazuhiro Ueda
  • Patent number: 11282633
    Abstract: An apparatus is provided which comprises: a planar dielectric surface, two or more conductive leads on the surface, the conductive leads extending away from the substrate surface, two or more conductive traces on the surface between the conductive leads, the traces substantially parallel to each other, and a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Fay Hua, Sidharth Dalmia, Zhichao Zhang
  • Patent number: 11276650
    Abstract: A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 15, 2022
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: YongIk Choi, Chris Chung, Michael Leary, Domingo Figueredo, Chang Kyu Choi, Sarah Haney, Li Sun