Abstract: A semiconductor device includes a substrate that has a first surface and a second surface on which a plurality of solder balls are provided, a semiconductor memory on the first surface of the substrate, a controller arranged on the first surface of the substrate, separated from the semiconductor memory along a first direction, and configured to control the semiconductor memory, a graphite sheet extending along the first direction above the controller and the semiconductor memory, and a first sealing material that seals the semiconductor memory, the controller, and the graphite sheet.

Abstract: A flexible foil-based package is disclosed which comprises at least one flexible foil substrate on which at least one electronic device is mounted in flip-chip mounting technology. The flexible foil substrate is bent so that a recess is created in which the electronic device is arranged. A casting compound is applied to cover the electronic device.

Abstract: A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.

Abstract: A method for forming a chip package structure is provided. The method includes disposing a first chip structure and a second chip structure over a wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The method includes disposing a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

Abstract: A package structure and method for forming the same are provided. The package structure includes a package component, and a dummy die disposed over the package component. The package structure includes a device die adjacent to the dummy die, and the device die includes a conductive pad, and the conductive pad is electrically connected to the package component.

Abstract: Fabrication of a bondwire inductor between connection pads of a semiconductor package using a wire bonding process is disclosed herein. To that end, the bondwire inductor is fabricated by extending a bondwire connecting two connection pads of the semiconductor package around a dielectric structure, e.g., a dielectric post or posts, disposed between the connection pads a defined amount. In so doing, the bondwire inductor adds inductance between the connection pads, where the added inductance is defined by factors which at least include the amount the bondwire extends around the dielectric structure. Such additional inductance may be particularly beneficial for certain semiconductor devices and/or circuits, e.g., monolithic microwave integrated circuits (MMICs) to control or supplement impedance matching, harmonic termination, matching biasing, etc.

Abstract: A spring electrode for a press-pack power semiconductor module includes a first electrode in contact with a power semiconductor chip, a second electrode arranged to face the first electrode, and a pressure pad which connects the first electrode and the second electrode and has flexibility in a normal direction of opposing surfaces of the first electrode and the second electrode. The opposing surfaces of the first electrode and the second electrode can be polygons of a pentagon or more, the pressure pad can be a cylindrical conductor or a plurality of wire conductors, and sides of the opposing surface of the first electrode and sides of the opposing surface of the second electrode corresponding to these sides are connected in parallel by the pressure pad.

Abstract: A package structure includes a base material, at least one electronic device, at least one encapsulant and a plurality of dummy pillars. The electronic device is electrically connected to the base material. The encapsulant covers the electronic device. The dummy pillars are embedded in the encapsulant. At least two of the dummy pillars have different heights.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.

Abstract: A semiconductor package includes a terminal pad having at least one first terminal lead structurally connected to the terminal pad, a semiconductor chip attached to an upper surface of the terminal pad by using a first adhesive, a heat radiation board attached to a lower surface of the terminal pad by using a second adhesive, and at least one second terminal lead electrically connected to the semiconductor chip. The second terminal lead is spaced apart from the terminal pad and is separated from the radiation board. The package further includes a metal clip electrically connecting the semiconductor chip to the second terminal lead, and a package housing covering parts of the first terminal lead, the second terminal lead, and the terminal pad. The package housing includes an adhesive spread space to expose the lower surface of the terminal pad.

Abstract: A module includes components on an upper surface and a lower surface of a substrate, a second sealing resin layer laminated on the upper surface of the substrate, a first sealing resin layer on the lower surface of the substrate, and terminal blocks on the lower surface of the substrate. Each of the terminal blocks is formed by integrating a plurality of connection conductors, each of the plurality of connection conductors including a terminal portion and a substrate connecting portion formed by bending an end portion of the connection conductor, and each of the terminal blocks forms an external connection terminal of the module or functions as a shield wall for the components. Each of the terminal blocks 6 can be formed by mounting a terminal assembly onto the lower surface of the substrate, sealing the terminal assembly with a resin, and removing connecting portions.

Abstract: A light emitting device includes a first light emitting element including a rectangular first light extraction surface, a second light emitting element including a rectangular second light extraction surface and emitting light having an emission peak wavelength different from an emission peak wavelength of the first light emitting element, and a light-transmissive member covering the first light extraction surface and the second light extraction surface. The light-transmissive member includes a first light-transmissive layer facing the first light extraction surface and the second light extraction surface, a wavelength conversion layer located on the first light-transmissive layer, and a second light-transmissive layer located on the wavelength conversion layer. The first light-transmissive layer contains a first matrix and first diffusive particles. The wavelength conversion layer contains a second matrix and wavelength conversion particles.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: A bottom side interposer provides a structurally balanced chip carrier module to reduce thermal warp and increase package robustness. The bottom side interposer is attached to the bottom of a chip carrier which carries semiconductor chips on the top side of the chip carrier. The top side of the chip carrier typically includes a top side interposer between the semiconductor chips and the chip carrier. The bottom side interposer has a coefficient of thermal expansion (CTE) that is similar to the chips and top side interposer, or tailored to have a CTE intermediate to the chips and the chip carrier. Pads on the bottom side interposer may be plated or fitted with solder balls to complete the module so the module can be connected to a printed circuit board.

Abstract: Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.

Abstract: Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wayer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.

Abstract: A packaging substrate and a semiconductor device comprising a semiconductor element, include a core layer and an upper layer disposed on the core layer, and the core layer includes a glass substrate as a core of the packaging substrate to improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a mother board to be closer to each other so that electrical signals are transmitted through as short a path as possible.

Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.