Patents Examined by A O Williams
  • Patent number: 11183645
    Abstract: An organic thin film that imparts an excellent electron injection property when it is used as an electron injection layer of an organic EL device and a method for producing the organic thin film are provided. An organic thin film at least includes: a first material which is an organic material having an acid dissociation constant pKa of 1 or greater; and a second material which transports an electron. The first material is at least one selected from the group consisting of tertiary amines, phosphazene compounds, guanidine compounds, heterocyclic compounds containing an amidine structure, hydrocarbon compounds having a ring structure, and ketone compounds.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: November 23, 2021
    Assignees: Nippon Hoso Kyokai, Nippon Shokubai Co., Ltd.
    Inventors: Hirohiko Fukagawa, Takahisa Shimizu, Katsuyuki Morii, Munehiro Hasegawa, Syun Gohda
  • Patent number: 11164740
    Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 2, 2021
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli
  • Patent number: 11164776
    Abstract: A method includes forming a metallic interconnect structure on a semiconductor substrate where the metallic interconnect structure comprises a plurality of metal lines with adjacent metal lines separated by a gap therebetween. The method further includes selectively depositing a first low-k dielectric material onto the semiconductor substrate and onto exposed surfaces of the metal lines of the metallic interconnect structure to form a barrier on at least the metal lines. The barrier is configured to minimize oxidation and diffusion of metal of the metal lines. The method also includes depositing a flowable second low-k dielectric material onto the semiconductor substrate to form a dielectric layer encapsulating the barrier and the metallic interconnect structure.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Son Nguyen, Takeshi Nogami, Thomas Jasper Haigh, Jr., Cornelius Brown Peethala, Matthew T. Shoudy
  • Patent number: 11164815
    Abstract: Techniques to enable bottom barrier free interconnects without voids. In one aspect, a method of forming interconnects includes: forming metal lines embedded in a dielectric; depositing a sacrificial dielectric over the metal lines; patterning vias and trenches in the sacrificial dielectric down to the metal lines, with the trenches positioned over the vias; lining the vias and trenches with a barrier layer; depositing a conductor into the vias and trenches over the barrier layer to form the interconnects; forming a selective capping layer on the interconnects; removing the sacrificial dielectric in its entirety; and depositing an interlayer dielectric (ILD) to replace the sacrificial dielectric. An interconnect structure is also provided.
    Type: Grant
    Filed: September 28, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Chun Kuen Cheng, Koichi Motoyama, Kisik Choi, Cornelius Brown Peethala, Hosadurga Shobha, Joe Lee
  • Patent number: 11158572
    Abstract: A package structure includes a base material, at least one electronic device, at least one dummy pillar and an encapsulant. The electronic device is electrically connected to the base material. The dummy pillar is disposed on the base material. The encapsulant covers the electronic device and a top end of the dummy pillar.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11152310
    Abstract: A microwave device includes: a multilayer resin substrate being a first multilayer resin substrate; an IC being a radio frequency circuit provided on the multilayer resin substrate and electrically connected to the multilayer resin substrate; a heat spreader provided on a side opposite to the multilayer resin substrate across the IC, and in contact with the IC; a mold resin covering the periphery of the IC and the heat spreader; and a conductive film covering the mold resin and the heat spreader, where an inner side of the conductive film is in contact with the heat spreader, and the conductive film is electrically connected to a ground via hole of the multilayer resin substrate.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukinobu Tarui, Makoto Kimura, Katsumi Miyawaki, Kiyoshi Ishida, Hiroaki Matsuoka
  • Patent number: 11145598
    Abstract: An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Nazila Dadvand, Archana Venugopal, Luigi Colombo
  • Patent number: 11145572
    Abstract: A semiconductor structure includes a semiconductor substrate, a porous semiconductor region within the semiconductor substrate, and through-substrate via (TSV) within the porous semiconductor region. The porous semiconductor region causes the semiconductor structure and/or the TSV to withstand thermal and mechanical stresses. Alternatively, the semiconductor structure includes a semiconductor buffer ring within the porous semiconductor region, and the TSV within the semiconductor buffer ring.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Newport Fab, LLC
    Inventor: David J. Howard
  • Patent number: 11145599
    Abstract: Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11133359
    Abstract: A thin, sheetlike, electronic, self-powered component including at least a display device and/or a sensor, as well as an energy source or a combination of the preceding is provided. Furthermore, the integration of this electrical component in existing products, especially printing and paper products, without the objects having to be damaged or destroyed is provided.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 28, 2021
    Assignee: INURU GMBH
    Inventors: Patrick Barkowski, Marcin Ratajczak
  • Patent number: 11133609
    Abstract: A semiconductor device includes: an insulation circuit substrate including a metal layer and an insulation substrate, the metal layer being formed on one surface of the insulation substrate, a connecting member having a cylindrical shape joined to the metal layer via a bonding material, a terminal pin inserted in the connecting member, and a reinforcement member having a cylindrical shape disposed on an outer periphery of the connecting member. The reinforcement member is made of a material having a hardness greater than that of the connecting member.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 28, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro Hinata, Tatsuo Nishizawa
  • Patent number: 11121095
    Abstract: A semiconductor device is provided that has high electromagnetic wave shielding properties while exhibiting good heat dissipation. The semiconductor device includes a semiconductor package bonded onto a circuit board, an electromagnetic wave absorbing layer covering surfaces of the semiconductor package other than a surface bonded to the circuit board, and an electromagnetic wave reflecting layer covering the electromagnetic wave absorbing layer on a side remote from the semiconductor package, in which the electromagnetic wave absorbing layer is made of resin containing magnetic particles or carbon, and the electromagnetic wave reflecting layer is made of resin containing conductive particles.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 14, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tomohiro Tanishita, Tsuneo Hamaguchi, Kiyoshi Ishida
  • Patent number: 11107703
    Abstract: Methods of manufacturing a biocompatible, hermetic feedthrough monolithically integrated with a biocompatible ribbon cable are described, as well as the resulting devices themselves. The hermetic feedthrough is created by placing glass over a mold of doped silicon or other material with a higher melting temperature than the glass and heating it to reflow the glass into the mold. The glass is then ground or otherwise removed to reveal a flat surface, and tiny pillars that were in the mold are isolated in the glass to form electrically conductive vias. The flat surface is used to cast a polymer and build up a ribbon cable, photolithographically or otherwise, that is monolithically attached to the vias.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 31, 2021
    Assignee: Neuralink Corp.
    Inventors: Vanessa M. Tolosa, Camilo A. Diaz-Botia, Supin Chen, Felix Deku, Yu Niu Huang, Mark J. Hettick, Zachary M. Tedoff
  • Patent number: 11101266
    Abstract: A 3D device including: a first level including first single crystal transistors overlaid by a second level including second single crystal transistors; a third level including third single crystal transistors, the second level is overlaid by the third level; a fourth level including fourth single crystal transistors, the third level is overlaid by the fourth level; first bond regions including first oxide to oxide bonds, where the first bond regions are between the first level and the second level; second bond regions including second oxide to oxide bonds, where the second bond regions are between the second level and the third level; and third bond regions including third oxide to oxide bonds, where the third bond regions are between the third level and the fourth level, where the second level, third level, and fourth level each include one array of memory cells, and where the one array of memory cells is a DRAM type memory.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 24, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11094641
    Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Patent number: 11094618
    Abstract: The invention relates to a modular element (2) comprising a stratification of first and second electroconductive plates (PH2, PB2) which are separated by an intermediate dielectric layer (CD2) and at least one electronic power switching chip (CP1, CP2) which is implanted between the first and second plates, the chip having a upper face comprising a first power electrode and a switching control electrode and a lower face comprising a second power electrode, and the first and second power electrodes being in electrical continuity respectively with the first and second plates.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 17, 2021
    Assignee: INSTITUT VEDECOM
    Inventor: Friedbald Kiel
  • Patent number: 11088112
    Abstract: A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The first die is disposed between the crystal and the substrate. An overmold encloses the first die and the crystal. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal, where the second die is disposed on an opposite side of the substrate from the first die and the crystal.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 10, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Darren Roger Frenette, George Khoury, Leslie Paul Wallis
  • Patent number: 11081431
    Abstract: A circuit device includes a first conductive plate and a second conductive plate each having a belt-shaped portion arranged side-by-side with each other, a third conductive plate having a belt-shaped portion is arranged side-by-side with and spaced apart from the other side portion of the first conductive plate, a first circuit component having a first terminal connected to the first conductive plate and a second terminal connected to the second conductive plate, a second circuit component having a first terminal connected to the first conductive plate and a second terminal connected to the third conductive plate, a first external connection portion provided at the belt-shaped portion of the first conductive plate, and a second external connection portion provided at the belt-shaped portion of the second conductive plate or a third external connection portion provided at the belt-shaped portion of the third conductive plate.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 3, 2021
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Jun Ikeda
  • Patent number: 11075144
    Abstract: Provided is a cooler having high cooling efficiency and low pressure loss of fluid. A cooler includes: a flow-channel part at least including a plate-like fin (top plate) and a plate-like fin (bottom plate); and a continuous groove-like flow channel defined between the top plate and the bottom plate to flow fluid, the cooler being configured to cool semiconductor elements. When the flow-channel part is viewed from the direction parallel to the top plate and intersecting the flow channel, the flow channel has a corrugated shape so that a face of the flow channel closer to the top plate and a face of the flow channel closer to the bottom plate bend in a synchronized manner toward the top plate and the bottom plate.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 27, 2021
    Assignees: FUJI ELECTRIC CO., LTD., WASEDA UNIVERSITY
    Inventors: Ryoichi Kato, Hiromichi Gohara, Yoshinari Ikeda, Tomoyuki Miyashita, Yoshihiro Tateishi, Shunsuke Numata
  • Patent number: 11069614
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang