Patents Examined by A. Pyonin
  • Low voltage junction and high voltage junction optimization for flash memory
    Patent number: 6159795
    Abstract: An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: December 12, 2000
    Assignees: Advanced Micro Devices, Inc., Fujitsu Limited
    Inventors: Masaaki Higashitani, Hao Fang, Narbeh Derhacobian