Patents Examined by A. Roberts
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Patent number: 5822214Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.Type: GrantFiled: August 21, 1995Date of Patent: October 13, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriv B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
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Patent number: 5706475Abstract: An information processing system for consulting centralized information originating in operational applications including a server and a plurality of microcomputers that issue requests to the server. The server includes data stored in the form of files and a metadictionary developed around a plurality of tables specific to the documentation and the administration of the system. Notably, the data is organized in domains, subdomains and functions, and are analyzed by a logical process contained in the metadictionary, which includes axes and indicators that describe the applications. The logical process makes it possible, at the moment the data to be imported into the server is defined, to create tables that contain the data of complementary tables, called consolidation tables, to authorize a generic response to all the requests made of the data and to optimize access performance.Type: GrantFiled: June 2, 1995Date of Patent: January 6, 1998Assignee: Bull, S.A.Inventors: Gabriel Entressangle, Claude Paoli, Jean Dalle Rive
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Patent number: 5675522Abstract: In order to divide an analyzing region in a semiconductor device into a plurality of fractional elements of a predetermined configuration, the analyzing region is initially divided into an arbitrary number of the fractional elements. With respect to a newly added nodal point, the fractional elements enclosing the new nodal point within a circumscribing range thereof are extracted as objective fractional elements for further division. Among the extracted fractional elements, specific fractional element having the perimetric fraction located within a predetermined modifying the perimeter of the fractional element group consisted of the extracted fractional elements. The fractional elements are re-establishes on the basis of the modified perimeter and the new nodal point.Type: GrantFiled: June 11, 1996Date of Patent: October 7, 1997Assignee: NEC CorporationInventor: Yutaka Akiyama
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Patent number: 5652872Abstract: A computer system emulates segment bounds checking with a paging system. Pages entirely within a segment are designated as `clear pages`, while the first and last pages containing segment bounds may be partially-valid pages. The computer system has a memory with a segment descriptor table and an active segment descriptor cache. The active segment descriptor cache holds a copy of the segment descriptors for the active segments in a central processing unit (CPU). The active segment descriptor cache also hold the first and last clear page numbers and the first and last linear address offsets for the active segment. A software segment load routine copies portions of the segment descriptor from the segment descriptor table to the active segment descriptor cache when a user program loads a new segment. Only the segment base address is copied to the CPU die; the segment limit and selector need not be stored on the CPU die.Type: GrantFiled: May 8, 1995Date of Patent: July 29, 1997Assignee: Exponential Technology, Inc.Inventors: David E. Richter, James S. Blomgren
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Patent number: 5634113Abstract: A method used by a digital computer for generating a preferred processing order of the vertices in a directed graph. The method also detects any cycles that exist in the directed graph. The vertices of the directed graph represent components of a system and the arcs represent the interrelationships between components. Each arc is defined by a vertex pair consisting of a starting vertex and an ending vertex. Each vertex is either assigned or unassigned to a processing order and marked as either a leaf vertex or a non-leaf vertex. The method includes traversing the set of arcs of the directed graph and marking the starting vertex as a non-leaf vertex for each arc whose ending vertex is unassigned, traversing the set of vertices and for each vertex that is unassigned and a leaf vertex, assigning the vertex to the processing order; and for each vertex that is unassigned and a non-leaf vertex, marking it as a leaf vertex.Type: GrantFiled: December 13, 1994Date of Patent: May 27, 1997Assignee: Unisys CorporationInventor: John T. Rusterholz