Abstract: A method and apparatus for defining a system design specification by using a finite set of templates that have a format for accepting a set of system expression such that a selected template, when filled with the system expressions, defines an intended behavioral attribute of the system. In one illustrative embodiment, each template has a set of qualifiers and a set of entry blanks, wherein each qualifier is associated with an entry blank. In such an embodiment, the set of entry spaces may comprise a fulfilling condition entry space for accepting a system expression that defines a required or assumed event of the system model, an enabling condition entry space for accepting a system expression that defines a precondition for starting a check of the required or assumed event, and a discharging condition entry space for accepting a system expression that defines a condition after which said fulfilling condition is no longer required or assumed by the system model.

Abstract: A hardware verification module performs simulation for hardware verification with input from an RT-level processor model and an RT-level hardware description. All abstraction module abstracts from the RT-level hardware description on a processor input/output instruction operation level to generate an abstracted description describing an instruction-level hardware description. A software verification module performs simulation for software verification with input from an instruction-level processor model and the abstracted description.

Abstract: A physical process is simulated by storing in a memory state vectors for voxels. The state vectors include entries that correspond to particular momentum states of possible momentum states at a voxel. Iinteraction operations are performed on the state vectors. The interaction operations model interactions between elements of different momentum states. For a particular state vector, the interaction operations include performing energy-exchanging interaction operations that model interactions between elements of different momentum states that represent different energy levels. A rate factor for the voxel represented by the particular state vector affects a degree to which energy-exchanging interaction operations cause a transfer of elements from states representing lower energy levels to states representing higher energy levels, rather than from states representing higher energy levels to states representing lower energy levels.

Abstract: An emulator system capable of solving a problem of a conventional emulator system in that it requires a gate array for executing a port function of a peripheral emulation chip because external pins of the peripheral emulation chip cannot achieve the port function required in a peripheral emulation mode. The present emulator system has at least two peripheral emulation chips. Each peripheral emulation chip includes a core block for controlling buses, a peripheral function block for achieving functions of a peripheral device, a mode setting circuit for setting a normal mode enabling the core block or the peripheral emulation mode enabling the peripheral function block, external pins, and a link switching circuit for selecting one of the connections of the external pins with the buses and with the peripheral function block.

Abstract: A linear feedback shift register (LFSR) of interest is modelled in software by replicating the LFSR in at least two identically configured model LFSRs. One model LFSR contains only the higher order initial bits of the LFSR of interest, with zeroes in the lower order bit positions, and the other model LFSR has only the lower order bits, with zeroes in the higher order bit positions. The model LFSRs are represented by respective tables of model LFSR output values that would be produced after a predetermined number of register shifts. The tables are accessed based on the initial value of the LFSR of interest, and the results of one table are combined with the results of the other table using an exclusive OR operator to thereby determine the output of the LFSR of interest.

Abstract: A system is provided for optimizing a network plan. The system includes a memory which stores information specifying a network plan, a plurality of constraints, and a plurality of interaction coefficients. Each interaction coefficient corresponds to particular constraint. A processor is coupled to the memory. The processor is operable to determine whether the network plan violates any of the constraints, modify the network plan in order to resolve a violation of any constraint, and update a corresponding interaction coefficient in order to reflect an impact upon the network plan caused by the resolution of a violation.

Abstract: A logic circuit design apparatus capable of designing scan circuits for uses peculiar to the logic circuit and scan circuits for test pattern generation simplification with ease is disclosed. The logic circuit design apparatus comprises a storage part, an acquisition part, a user resister design part, and a data chain design part. The storage part stores a circuit data of a logic circuit whose logic design for normal operation. The acquisition part acquires a design data which specifies a user resister that is a scan circuit to be designed on the logical circuit whose circuit data is stored in the storage part. The user resister design part designs a user resister corresponding the design data acquired by the acquisition part. The data chain design part designs a data chain which is a scan circuit for test pattern generation simplification by utilizing the user register designed by the user register design part.

Abstract: An ion-implantation simulation method including (1) a step of generating orthogonal meshes for a multilayer-structure substrate, (2) a step of taking out a longitudinal strip, (3) a step of determining a function representing an impurity distribution in the longitudinal strip, (4) a step of integrating the function representing the impurity distribution in the range of each cell in the longitudinal strip, and dividing the integration value by the integration range to set the division result as the impurity concentration in the cell, (5) a step of taking out a transverse strip, (6) a step of determining a function of re-distributing the impurity distribution in the transverse strip in the transverse direction, and (7) a step of integrating the re-distributing function in the range of each cell in the transverse direction, dividing the integration result by the integration range and setting the division result as the impurity concentration in the cell.

Abstract: An apparatus and method for determining the types of expansion cards connected to the expansion slot connectors of a computer system. Detect signals are provided to decode logic for determining the types of expansion cards connected to the computer system. If the expansion cards are compatible the decode logic produces an output power supply signal that indicates what the voltage level should be for the power supply to the cards. If the cards are incompatible, the decode logic may not provide power to any of the cards or only provide power to some of the cards that are compatible. For computers that allow expansion cards to connect to the computer while the computer is powered on, hot-plug logic cooperates with the decode logic to establish power and communication with newly connected interface cards. The connectors in the computer do not include keys and thus interface cards without keys, as well as cards with different types of key arrangements can be connected to and communicate with the computer.

Abstract: An improved method and architecture for mapping data between fixed structure datasets defined by different computer formats. The method employs a simple intuitive mapping template which operates from an embedded knowledge of the structure rules for the data being exchanged. The mapping template is flexible and allows the details of the data manipulation required for translation to be expressed by a layperson, and without the requirement that they define the entire message structure in every detail. It is also possible for the mapping template(s) themselves to be transmitted along with the datasets to facilitate conversion between data formats.

Abstract: Method and apparatus for creating the appearance of a network device and its communications, and in particular, an SNMP agent and its SNMP communications. A device dataset contains a plurality of counter variables having instance values which change over time and describe the behavior of the device on the network. A characterization file is created from the device dataset based on correlations among the variables and their instance values. The characterization file is used to generate predicted instance values for a simulated device.

Abstract: The composition of an alloy is inhomogeneous, so that the Fermi level of electrons in the surface of the alloy differs depending upon positions. It is accordingly considered that a part susceptible to corrosion and a part less susceptible thereto will coexist in the alloy. The corrosion rate of the alloy is indicated as the exponential function of a potential difference (.DELTA..PHI..sub.H) within an electric double layer. The potential difference remains unchanged as long as the Fermi level lies within the forbidden band of the electrons. However, in a range in which the Fermi level falls within the valence band of the electrons, the lowering thereof leads to the increase of the potential difference.

Abstract: An address shadow feature and methods of using the same. A slave controller of the present invention includes an address register coupled to receive a device address from a secondary bus interface. A match circuit is coupled to the address register and compares the device address to a shadow address, generating a match signal upon detection of a match between the shadow address and the device address. An interrupt generation circuit generates an interrupt signal in response to the match signal.

Abstract: Disclosed is a method of improved grid generation for semiconductor device simulation. In particular, the invention includes a simple method for locating critical interfaces (e.g., oxide-silicon interfaces) and then utilizing the information to generate finer mesh elements near those boundaries where device behavior is most critical. The method of identifying critical interfaces includes the steps of examining the boundary data for each material region in the device, and then generating normal lines between adjacent boundaries to identify "thin" regions, which are generally associated with the critical interfaces. Once this occurs, a recursive subdivision algorithm may be utilized to generate a grid whose element dimensions are dependent upon their proximity to identified critical regions.

Abstract: A network emulator capable of emulating an entire restoration network improves the process of testing a centralized system for monitoring, restoration, and control of the system. The network emulator has a segmented process architecture such that emulation of the aspects of the restoration network is realized with discrete process components, including an alarm generator, an alarm feeder and a communications emulator. The alarm generator reads in a user-defined network event, analyzes network topology data to determine the impact of the event, and generates an alarms file specifying the alarms generated by the emulated network in response to the event. The alarm feeder reads additional user input specifying the nature of the event, reads the alarms file and determines the sequencing and timing of each alarm. The alarm feeder then feeds the alarms, in specific order and time intervals, to the communications emulator.

Abstract: The present invention provides a device simulation method comprising at least the steps of: inputting a geometry of a semiconductor device, a donor and an acceptor impurity concentrations at each point inside the semiconductor device and also terminal voltages of the semiconductor device (step S101); setting initial values by obtaining electron concentrations n, and n.sub.J and also hole concentrations p.sub.I and p.sub.J with respect to given points I and J respectively inside the semiconductor device and also a potential at each point (step S102); obtaining a voltage difference .PSI..sub.dd across a prescribed segment dd along a segment IJ connecting the points I and J (step S103); calculating an electron current density J.sub.eIJ of the segment IJ by an equation J.sub.eLJ =C.sub.eI .multidot.A(.PHI..sub.edd)-C.sub.eJ .multidot.A(-.PHI..sub.edd) using a constant C.sub.eI dependent on the electron concentration n.sub.J, a constant C.sub.eJ dependent on the electron concentration n.sub.

Abstract: A method for the design of a golf club head includes the selection, by the designer, of dimensions which define the basic shape of the golf club head. Once the basic shape of the club head is defined, critical points on the golf club head may be located. Once the basic shape and the critical points are known, a model of the basic shape may then be displayed. In addition, the method may further include the selection of desired mass properties, types of mass constraints and back-weighting parameters, all of which are determined by the designer. These specifications, in addition to the basic shape of the club head permit the design of back-weighting of the club head. Once the back-weighting has been designed, the final solid model of the golf club head, which includes the basic shape and back-weighting, may be displayed.

Abstract: In order to reduce the amount of work that must be done to implement a revised circuit design in physical circuitry, portions of the new design that are the same as a previously implemented design are identified. This preferably involves several different, successively applied approaches to attempting to find matching circuit components in the new and old designs. Connections that have changed between otherwise unchanged components are also identified. The physical circuit implementation of the unchanged portions of the old design can be reused in the implementation of the new design, thereby reducing the amount of new physical circuit implementation work that must be done.

Abstract: A circuit transformation software module incorporating the teachings of the present invention is provided to an otherwise conventional emulation system. The circuit transformation software module takes a circuit design as input and transforms it into a "new" circuit design in accordance to a plurality of circuit primitive transformation rules of the present invention, which embodies a circuit state encoding scheme of the present invention. This "new" circuit design when "realized" on the otherwise conventional emulation system in a conventional manner, allows the original circuit design to be simulated on the emulation system, i.e., the response of the original circuit design under various unknown and uncertain conditions can be simulated. As a result, correctness of the original circuit design's responses under these conditions can be correctly ascertained. Additionally, reliability/accuracy of fault simulation results is improved.

Abstract: A simulation apparatus for simulating and optimizing a configuration of a sputtering apparatus including a target surface temperature calculating unit for calculating a temperature of a target surface in consideration of cooling of the target, an atom initial velocity calculating unit for calculating an initial velocity of atoms within the target based on the calculated target surface temperature, an ion incidence rate calculating unit for calculating an incidence rate of the incident ions into the target to determine a position at which the incident ions collide against the target, an atom trajectory calculating unit for obtaining trajectories of atoms within the target based on each of calculation results and a sputtered atom ejection angle distribution unit for extracting sputtered atoms based on the calculation results to obtain ejection angle distribution.