Patents Examined by A. Sefer
  • Patent number: 11031556
    Abstract: In an embodiment, a method includes: growing a phase change material on a platform configured for a semiconductor workpiece process; setting the phase change material to an amorphous state; performing the semiconductor workpiece process within a semiconductor processing chamber; and measuring resistance across two points along the phase change material.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Mao Chen, Hung-Jen Hsu
  • Patent number: 11031384
    Abstract: Provided is an integrated circuit including a semiconductor substrate, a plurality of gate lines and a plurality of metal lines. The plurality of gate lines are formed in a gate layer above the semiconductor substrate, where the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the second direction. The plurality of metal lines are formed in a conduction layer above the gate layer, where the plurality of metal lines are arranged in the first direction and extend in the second direction. 6N metal lines and 4N gate lines form a unit wiring structure where N is a positive integer and a plurality of unit wiring structures are arranged in the first direction. Design efficiency and performance of the integrated circuit are enhanced through the unit wiring structure.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-su Kim
  • Patent number: 11024616
    Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Long-Hua Lee, Szu-Wei Lu, Ying-Ching Shih, Kuan-Yu Huang
  • Patent number: 11016055
    Abstract: Structures for transistor-based sensors and related fabrication methods. A layer stack is formed that includes a semiconductor layer and a cavity. A transistor is formed that has a gate electrode over the layer stack, and an interconnect structure is formed over the layer stack and the transistor. First and second openings are formed that extend through the metallization levels of the interconnect structure and the semiconductor layer to the cavity. The first opening defines a fluid inlet coupled to the cavity, and the second opening defines a fluid outlet coupled to the cavity.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 25, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Humberto Campanella-Pineda, Qizhi Liu, Vibhor Jain, You Qian, Joan Josep Giner de Haro
  • Patent number: 11015248
    Abstract: Described herein is a technique capable of suppressing a deviation in a thickness of a film formed on a substrate. According to one aspect of the technique of the present disclosure, a substrate processing apparatus includes a substrate retainer capable of supporting substrates; a cylindrical process chamber including a discharge part and supply holes; partition parts arranged in the circumferential direction to partition supply chambers communicating with the process chamber through the supply holes; nozzles provided with an ejection hole; and gas supply pipes. The supply chambers includes a first nozzle chamber and a second nozzle chamber, the process gas includes a source gas and an assist gas, the nozzles includes a first nozzle for the assist gas flows and a second nozzle disposed in the second nozzle chamber and through which the source gas flows, and the first nozzle is disposed adjacent to the second nozzle.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 25, 2021
    Assignee: Kokusai Electric Corporation
    Inventors: Hironori Shimada, Daigi Kamimura
  • Patent number: 11011521
    Abstract: Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sevim Korkmaz, Devesh Dadhich Shreeram, Srinivasan Balakrishnan, Dewali Ray, Sanjeev Sapra, Paul A. Paduano
  • Patent number: 10998243
    Abstract: A method of manufacturing a semiconductor device includes forming a field plate on an insulating film covering a transistor, the field plate being electrically coupled to a gate of the transistor via the insulating film, and the transistor being located on a substrate, forming a silicon nitride protective film covering the insulating film and the field plate, forming a silicon oxide base film on the silicon nitride protective film, and forming a MIM capacitor on the silicon oxide base film. The MIM capacitor includes a first electrode, a dielectric film and a second electrode which are stacked in an order. Forming the MIM capacitor includes performing wet etching on the silicon oxide base film on the field plate after forming the dielectric film.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: May 4, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Takuma Nakano, Tomoki Maruyama
  • Patent number: 10998402
    Abstract: Crystal lattice vacancies are generated in a pretreated section of a semiconductor layer directly adjoining a process surface. Dopants are implanted at least into the pretreated section. A melt section of the semiconductor layer is heated by irradiating the process surface with a laser beam activating the implanted dopants at least in the melt section.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 4, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alexander Breymesser, Hans-Joachim Schulze, Holger Schulze, Werner Schustereder
  • Patent number: 10998395
    Abstract: An organic light-emitting display device comprises a substrate comprising a plurality of sub-pixels, each of the sub-pixels having an emission area and a non-emission area provided to surround the emission area; an auxiliary line disposed in the non-emission area; a first insulating film having a first hole configured to expose a portion of the auxiliary line; an auxiliary line connection pattern disposed on the first insulating film having a protruding portion protruding towards a center of the first hole and overlapping the auxiliary line; at least one bump disposed on the auxiliary line within the first hole and adjacent to the protruding portion of the auxiliary line connection pattern; and a bank having a second hole larger than the first hole to expose the protruding portion of the auxiliary line connection, thereby lowering resistance of a cathode covering a plurality of sub-pixels and preventing lateral current leakage between the sub-pixels through a change of the connection structure between the aux
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: May 4, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Joon-Soo Han, Im-Kuk Kang, Jung-Woo Ha
  • Patent number: 10988372
    Abstract: A method includes forming a first mask on a first portion of a first surface of a substrate, forming a second mask on the first mask and further forming the second mask on a second portion of the first surface of the substrate, and etching an exposed portion of the first surface of the substrate and removing the second mask. According to some embodiments, an exposed portion of the first surface of the substrate is etched and the first mask is removed. An oxide layer is formed on the first surface of the substrate. A third mask is formed on the oxide layer except for a portion of the oxide layer corresponding to bumpstop features. The portion of the oxide layer corresponding to the bumpstop features is removed. An exposed portion of the first surface of the substrate is etched and the third mask is removed.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: April 27, 2021
    Assignee: InvenSense, Inc.
    Inventor: Dongyang Kang
  • Patent number: 10991597
    Abstract: A method of fabricating a semiconductor device is provided in which an adhesive layer is disposed on a first surface of a first semiconductor substrate. A carrier substrate is provided on the first surface of the first semiconductor substrate, and the carrier substrate is separated from a surface of the adhesive layer while the adhesive layer is still attached to the first surface of the first semiconductor substrate.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Kyung-Hak Lee, Jaeyong Park, Jun-su Lim, Sungil Cho
  • Patent number: 10991910
    Abstract: An encapsulation film covering a light emitting element includes: a first inorganic layer covering the light emitting element; an organic layer formed on the first inorganic layer; a second inorganic layer formed on the organic layer; and a third inorganic layer formed on the second inorganic layer. The peripheral end face of the second inorganic layer is aligned with the peripheral end face of the organic layer. The third inorganic layer covers the peripheral end face of the first inorganic layer or the peripheral end face of the second inorganic layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 27, 2021
    Assignees: SHARP KABUSHIKI KAISHA, SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Takashi Ochi, Tohru Sonoda, Takeshi Hirase, Katsuhiko Kishimoto
  • Patent number: 10991852
    Abstract: A transparent light-emitting display film includes a transparent substrate in a form of film, a transparent electrode on a first side of the transparent substrate, a through hole formed to penetrate the transparent substrate in a direction perpendicular to a plane of the transparent substrate, a light-emitting device mounted in the through hole, and a connection member configured to electrically connect the transparent electrode and the light-emitting device.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 27, 2021
    Assignees: JMICRO INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY (KAIST)
    Inventors: Seung Seob Lee, Dong Jin Kim, Munhyung Jo, Jung-woo Lee
  • Patent number: 10985195
    Abstract: The present disclosure relates to an array substrate. The array substrate includes an active area; and a non-active area located outside the active area. The non-active area includes a flexible substrate having a surface provided with a number of grooves, and a peripheral metal wiring located in the number of grooves.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: April 20, 2021
    Assignee: KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Mingxing Liu, Deqiang Zhang, Dongyun Lv, Xuliang Wang, Shuaiyan Gan, Feng Gao
  • Patent number: 10978409
    Abstract: A semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface, a first semiconductor chip on the first surface of the first substrate, a second semiconductor chip on the first surface of the first, a stiffener on the first semiconductor chip and the second semiconductor chip, and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof. The first semiconductor chip is connected to a first group of first pads of the plurality of first pads. The second semiconductor chip is connected to a second group of first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least a sidewall of each of the first and second semiconductor chips and the stiffener.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyong Soon Cho
  • Patent number: 10964659
    Abstract: A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen, Tsung-Yuan Yu
  • Patent number: 10964860
    Abstract: A method of packaging a semiconductor illumination module is provided. The method includes the following steps. In a step (a), a substrate is provided. The substrate is selected from one of a flexible printed circuit board, a metal core circuit board, a printed circuit board or a ceramic printed circuit board. The substrate includes a solder mask layer with an opening, and the opening has a width R. In a step (b), a light-emitting element is installed in the opening. In a step (c), an encapsulant injection device is used to inject a packaging encapsulant into the opening. In a step (d), a sealed lens structure is formed to cover the light-emitting element, wherein the sealed lens structure has a height h.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 30, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Hung-Wei Kuo, Ya-Chin Tu, Chung-Yuan Chen
  • Patent number: 10964662
    Abstract: A method of transferring a micro device is provided. The method includes: aligning a transfer plate with the micro device thereon with a receiving substrate having a contact pad thereon such that the micro device is above or in contact with the contact pad; moving a combination of the transfer plate with the micro device thereon and the receiving substrate into a confined space with a relative humidity greater than or equal to about 85% so as to condense some water between the micro device and the contact pad; and attaching the micro device to the contact pad.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 30, 2021
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10964916
    Abstract: Direct pixel-by-pixel phase engineering in a SLM is an effective method for the holographic fabrication of graded photonic super-quasi-crystals with desired disorder and graded photonic super-crystals with rectangular unit-cells. Multiple levels of filling fractions of dielectric in the crystal have been created in the graded regions. Fabrication of these graded photonic super-crystals and super-quasi-crystals with small feature size is possible, using a laser projection system consisting of integrated spatial light modulator and reflective optical element.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: March 30, 2021
    Assignee: UNIVERSITY OF NORTH TEXAS
    Inventors: Yuankun Lin, David Lowell, Safaa Hassan
  • Patent number: 10950533
    Abstract: A through electrode substrate includes: a substrate having a first surface and a second surface facing the first surface; through electrodes penetrating through the substrate; and a first capacitor including a first conductive layer, an insulating layer, and a second conductive layer, arranged on the first surface side of the substrate, and electrically connected with at least one of the through electrodes. The first conductive layer is arranged on the first surface side of the substrate and is electrically connected with the through electrode. The insulating layer includes a first part and a second part and is arranged on the first conductive layer. The second conductive layer is arranged on the insulating layer. The first part is arranged between the first conductive layer and the second conductive layer. The second part covers at least a part of a side surface of the first conductive layer.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 16, 2021
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Takamasa Takano, Satoru Kuramochi