Patents Examined by A. Sefer
  • Patent number: 10475881
    Abstract: Crystal lattice vacancies are generated in a pretreated section of a semiconductor layer directly adjoining a process surface. Dopants are implanted at least into the pretreated section. A melt section of the semiconductor layer is heated by irradiating the process surface with a laser beam activating the implanted dopants at least in the melt section.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Hans-Joachim Schulze, Holger Schulze, Werner Schustereder
  • Patent number: 10475882
    Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation <011>. Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation <011>, and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation <010> and the crystal orientation <011>.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: November 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeaki Saito, Yoshito Nakazawa, Hitoshi Matsuura, Yukio Takahashi
  • Patent number: 10475760
    Abstract: A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen, Tsung-Yuan Yu
  • Patent number: 10468586
    Abstract: An electronic device is provided, including: a first drive electrode; a second drive electrode that is spaced apart from the first drive electrode; and a topological insulator that contacts both of the first drive electrode and the second drive electrode and has magnetism, wherein the topological insulator includes a first region having a first coercivity and a second region having a second coercivity that is different from the first coercivity. A fabrication method of a topological insulator is also provided, including: preparing a topological insulator having magnetism and a first coercivity; and forming a second region having a second coercivity that is different from the first coercivity by irradiating a partial region of the topological insulator with ions.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: November 5, 2019
    Assignee: RIKEN
    Inventors: Ryutaro Yoshimi, Masataka Mogi, Naoto Nagaosa, Masashi Kawasaki, Yoshinori Tokura, Wataru Koshibae
  • Patent number: 10468475
    Abstract: The invention discloses a display panel and a display device. The display panel including a fold area, and at least one non-fold area proximate to the fold area, the display panel includes: an underlying substrate, a plurality of light-emitting elements, and a plurality of pixel circuit units arranged on the underlying substrate, which are arranged in the non-fold area; and the non-fold area includes at least one first area and second area; and there are a plurality of the pixel circuit units arrayed respectively in the first area and the second area, the first area is adjacent to the fold area, the second area is located on the side of the first area away from the fold area, and the distribution density of the pixel circuit units in the first area is higher than or equal to the distribution density of the pixel circuit units in the second area.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 5, 2019
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Xiaobo Cai
  • Patent number: 10468391
    Abstract: An inorganic light-emitting diode (iLED) display comprises a separate, independent, and distinct display substrate having a display area. A plurality of spatially separated pixels are distributed on or over the display substrate in the display area. Each pixel includes a group of two or more spatially separated iLEDs each having an iLED substrate separate, independent, and distinct from the display substrate. The two or more iLEDs are electrically connected in common to emit light together in response to a control signal. The pixels can include multiple groups of two or more iLEDs, each group of iLEDs can emit a different color of light to make a full-color display. The iLED display can be a passive-matrix display or include a pixel controller in an active-matrix configuration. The iLEDs and pixel controller can be provided on a pixel substrate disposed on the display substrate.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: November 5, 2019
    Assignee: X-Celeprint Limited
    Inventor: Ronald S. Cok
  • Patent number: 10457544
    Abstract: A MEMS transducer for interacting with a volume flow of a fluid includes a substrate including a cavity, and an electromechanical transducer connected to the substrate in the cavity and including an element deformable along a lateral movement direction, wherein a deformation of the deformable element along the lateral movement direction and the volume flow of the fluid are causally related.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 29, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Harald Schenk, Holger Conrad, Matthieu Gaudet, Klaus Schimmanz, Sergiu Langa, Bert Kaiser
  • Patent number: 10461184
    Abstract: A semiconductor device includes a semiconductor substrate having a first source or drain (S/D) region and a channel. The channel includes a first semiconductor material having a first band gap, and extends vertically from a lower channel portion formed on the first S/D region to an upper channel portion located opposite the lower channel portion. A gate structure is around sidewalls of the channel, and a second S/D region is on the upper channel portion. A band-gap enhancing region is interposed between the second S/D region and the channel. The band-gap enhancing region includes a second semiconductor material having a second band gap that is greater than the first band gap to reduce a gate-induced-drain leakage (GIDL) between the second S/D region and the channel.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee
  • Patent number: 10461218
    Abstract: A semiconductor device according to an embodiment includes: a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, and a plurality of recesses exposing a lower portion of the first conductive semiconductor layer; at least one pad arranged outside the light emitting structure and arranged to be adjacent to at least one edge; and a plurality of insulation patterns arranged in the recesses and extending to a lower surface of the light emitting structure, in which widths of the plurality of insulation patterns are reduced as the insulation patterns become further away from the pad. The semiconductor device according to the embodiment may prevent a current from being focused on a recess area adjacent to the pad.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 29, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Ji Hyun Koo, Dae Hee Lee, Jung Wook Lee
  • Patent number: 10454056
    Abstract: The present invention provides an organic light emitting device including a light emitting layer comprising a compound represented by Chemical Formula 1 and an electron transport layer comprising a compound represented by Chemical Formula 2, and having improved driving voltage and efficiency.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 22, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Min Seung Chun, Sang Young Jeon, Boon Jae Jang, Minwoo Choi, Hyeon Soo Jeon
  • Patent number: 10454041
    Abstract: The present invention relates to a process to produce compounds of the formula (1) which are suitable for use in electronic devices, as well as to intermediate compounds of formula (Int-1) and compounds of formula (1-1) and (1-2) obtained via the process. These compounds are particularly suitable for use organic electroluminescent devices. The present invention also relate to electronic devices, which comprise these compounds.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: October 22, 2019
    Assignee: Merck Patent GmbH
    Inventors: Teresa Mujica-Fernaud, Elvira Montenegro
  • Patent number: 10453820
    Abstract: Semiconductor assemblies using edge stacking and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise stacked semiconductor packages including a base substrate having a base surface, a side substrate having a side surface orthogonal to the base surface, and a die stack disposed over the base surface and having an outermost die with an outermost surface orthogonal to the side surface. The side substrate can be electrically coupled to the die stack via a plurality of interconnects extending from the side surface of the side substrate to the first surface of the first substrate or the third surface of the outermost die. The semiconductor packages can further comprise a conductive material at an outer surface of the side substrate, thereby allowing the semiconductor packages to be electrically coupled to neighboring semiconductor packages via the conductive material.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 10424528
    Abstract: An assembly includes at least one heat emitting device and a continuous conformal cooling structure adhering directly to and conforming with surfaces of at least a portion of the at least one heat emitting device. The cooling structure may include a thermally-conductive, electrically-insulative layer adhering directly to surfaces of the at least one heat generating device to provide an electrically nonconductive, continuous, conformal layer covering all such surfaces. An inner metallization layer may be adhered directly to surfaces of at least a portion of the insulative layer. An outer metallization layer may be adhered directly to surfaces of the inner metallization layer to provide a thermally conductive layer covering such surfaces.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 24, 2019
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Feng Zhou, Yanghe Liu, Ercan Mehmet Dede
  • Patent number: 10417477
    Abstract: A display device with a display panel including a display area and a plurality of pixels arranged in the display area, a photosensor layer including a sensing area overlapping the display area and a plurality of photosensors arranged in the sensing area, a light-guiding layer arranged between the display panel and the photosensor layer and configured to include a plurality of light-transmission holes corresponding to the photosensors, respectively, and a light-condensing layer arranged between the display panel and the photosensor layer to overlap the light-guiding layer.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: September 17, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gwang Bum Ko, Do Ik Kim, Seung Hwan Chung, Sung Hwan Kim
  • Patent number: 10410867
    Abstract: An embodiment includes a system comprising: a first gate and a first contact that correspond to a transistor and are on a first fin; a second gate and a second contact that correspond to a transistor and are on a second fin; an interlayer dielectric (ILD) collinear with and between the first and second contacts; wherein (a) the first and second gates are collinear and the first and second contacts are collinear; (b) the ILD includes a recess that comprises a cap layer including at least one of an oxide and a nitride. Other embodiments are described herein.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Vyom Sharma, Rohan K. Bambery, Christopher P. Auth, Szuya S. Liao, Gaurav Thareja
  • Patent number: 10411124
    Abstract: A semiconductor structure includes a substrate, a III-Nitride intermediate stack including the protrusion propagation body situated over the substrate, a transition body over the III-Nitride intermediate stack, a III-Nitride buffer layer situated over the transition body, and a III-Nitride device fabricated over the group III-V buffer layer. The protrusion propagation body includes at least a protrusion generating layer and two or more protrusion spreading multilayers.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 10, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Chan Kyung Choi, Mihir Tungare, Peter Wook Kim
  • Patent number: 10410944
    Abstract: The present disclosure provides a semiconductor device for high efficiently releasing heat generated from a semiconductor element to the outside.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 10, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Isamu Nishimura
  • Patent number: 10410969
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 10, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng
  • Patent number: 10411143
    Abstract: A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: September 10, 2019
    Assignee: Sony Corporation
    Inventor: Naoyuki Sato
  • Patent number: 10411012
    Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: September 10, 2019
    Assignee: Apple Inc.
    Inventors: Jared L. Zerbe, Emerson S. Fang, Jun Zhai, Shawn Searles