Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.

Abstract: A semiconductor device includes a terminal, a first semiconductor chip, a second semiconductor chip located on the first semiconductor chip, a first pad located on the first semiconductor chip and electrically disconnected from a semiconductor circuit of the first semiconductor chip, a second pad located on the second semiconductor chip and electrically connected to a semiconductor circuit of the second semiconductor chip, a first wire electrically connecting the first terminal to the first pad, and a second wire electrically connecting the first pad to the second pad.

Abstract: In a semiconductor device, a first skirt portion molded from a first mold resin and a second skirt portion molded from a second mold resin are provided on a heat dissipating surface of a lead frame. Also, a thinly-molded portion is molded integrally with the second skirt portion from the second mold resin. According to this kind of configuration, adhesion between the thinly-molded portion and lead frame is high, and the semiconductor device with excellent heat dissipation and insulation is obtained.

Abstract: An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process.

Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.

Abstract: A method for depositing a layer on a semiconductor wafer by vapor deposition in a process chamber, involves removing native oxide from a surface of the wafer; and then depositing an epitaxial layer with a thickness of at least 40 ?m on the surface of the wafer by introducing a silicon containing gas and a carrier gas into the process chamber, wherein the flow rate of the silicon containing gas is lower than 10 standard liters per minute and the flow rate of the carrier gas is at least 40 standard liters per minute.

Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.

Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

Abstract: Semiconductor devices include a patterned dielectric layer overlaying a semiconductor substrate; a metal layer comprising copper disposed in the patterned dielectric layer; and a barrier layer formed at an interface between the dielectric layer and the metal layer, wherein the barrier layer is AlOxNy. The patterned dielectric may define a trench and via interconnect structure or first and second trenches for a capacitor structure. Also disclosed are processes for forming the semiconductor device, which includes subjecting the dielectric surfaces to a nitridization process to form a nitrogen enriched surface. Aluminum metal is then conformally deposited onto the nitrogen enriched surfaces to form AlOxNy at the aluminum metal/dielectric interface. The patterned substrate is then metalized with copper and annealed. Upon annealing, a copper aluminum alloy is formed at the copper metal/aluminum interface.

Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.

Abstract: A semiconductor device includes a semiconductor element, a circuit board, metal wires, and an expanding member. The circuit board has an upper surface and a lower surface opposite the upper surface. The metal wires are formed on at least one of the upper surface and the lower surface. At least two connection terminals are formed in a terminal formation surface of the semiconductor element which is disposed so as to face the upper surface of the circuit board. The expanding member is fixed to the terminal formation surface of the semiconductor element, has a larger coefficient of linear thermal expansion than the semiconductor element, and has a size larger than the interval between adjacent two of the at least two connection terminals.

Abstract: A display substrate, a method for manufacturing the display substrate, and a display device are provided. The display substrate includes a display area and a non-display area surrounding the display area. The non-display area of the display substrate includes a shading pattern, to prevent light from being transmitted through the non-display area.

Abstract: An interconnect substrate includes vertical connection channels around a cavity. The vertical connection channels are made of a combination of metal posts and metallized vias. The cavity includes a recess in a core layer and an aperture in a stiffener. The metal posts, disposed over the top surface of the core layer, are sealed in the stiffener and are electrically connected to a buildup circuitry adjacent to the bottom surface of the core layer. The minimal height of the metal posts needed for the vertical connection can be reduced by the amount equal to the depth of the recess. The buildup circuitry is electrically connected to the metal posts through the metallized vias.

Abstract: Various optoelectronic modules are described that include an optoelectronic device (e.g., a light emitting or light detecting element) and a transparent cover. Non-transparent material is provided on the sidewalls of the transparent cover, which, in some implementations, can help reduce light leakage from the sides of the transparent cover or can help prevent stray light from entering the module. Fabrication techniques for making the modules also are described.

Abstract: A semiconductor device includes a signal processing circuit configured to generate an output signal, an output pad, an output line connecting the signal processing circuit to the output pad, the output signal from the signal processing circuit being output from the output pad through the output line, a shorting pad formed in the output line, a switch connected between the shorting pad and the output pad, and configured to connect the signal processing circuit to the output pad when the switch is on, and disconnect the signal processing circuit from the output pad when the switch is off, and a wiring line connecting the shorting pad to the output pad.

Abstract: Embodiments of the present disclosure provide a touch display substrate and manufacturing method thereof. The method includes forming a touch signal line on a base substrate through patterning process; depositing a photoresist layer, and forming a first thickness photoresist layer, a second thickness photoresist layer and a photoresist layer opening area through patterning process, the touch signal line being located in the photoresist layer opening area; depositing a first insulating layer on the photoresist layer, the first insulating layer comprising a first area and a second area, wherein the first area is located on the first thickness photoresist layer, the second area is located on the second thickness photoresist layer and the photoresist layer opening area, the first area and the second area of the first insulating layer are disconnected; removing the photoresist layer and the first insulating layer located on the photoresist layer; and depositing a second insulating layer.

Abstract: A semiconductor light-emitting element including a first semiconductor layer of a first conductivity type; a light-emitting functional layer that includes first and second light-emitting layers; and a second semiconductor layer of a conductivity type opposite to the conductivity type of the first semiconductor layer. The first light-emitting layer has a first base layer with a composition subject to stress strain from the first semiconductor layer; a first quantum well layer that retains a segment shape of the first base segment; and a first barrier layer that has a flat surface flattened by embedding the first base layer and the first quantum well layer. The second light-emitting layer has a second base layer that has a composition subject to stress strain from the first barrier layer; a second quantum well layer that retains a segment shape of the second base segment; and a second barrier layer.

Abstract: Reliability of a plating process and reliability of a component manufactured through the plating process can be improved by suppressing peeling between plating layers formed by electroless plating. In a plating method, a plated component manufactured by the plating method, and a plating system 1 configured to manufacture the plated component by the plating method, a second electroless plating layer 39, which is made of a copper alloy and formed by the electroless plating, is formed on a surface of a first electroless plating layer 38 formed by the electroless plating. The first electroless plating layer 38 is a barrier layer configured to suppress diffusion of copper and is made of cobalt or a cobalt alloy. The second electroless plating layer 39 is a seed layer for forming an electrolytic plating layer of copper on a surface thereof and is made of an alloy of copper and nickel.

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

Abstract: A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface if the layers. The second magnetic layer has a saturation magnetization lower than that of the first magnetic layer, and an interfacial magnetic anisotropy energy density (Ki) at the interface between the first magnetic layer and the first non-magnetic layer is greater than that of an interface between the first non-magnetic layer and second magnetic layers if being disposed adjacent each other.