Patents Examined by A. Sefer
  • Patent number: 11462480
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Johanna M. Swan
  • Patent number: 11456201
    Abstract: A semiconductor substrate according to an embodiment includes a substrate having a first substrate surface, the substrate having a first outer diameter; a metal layer provided on the first substrate surface, the metal layer having a second outer diameter smaller than the first outer diameter; a first adhesive tape having a ring shape, the ring shape having a third outer diameter smaller than the first outer diameter and larger than the second outer diameter, the ring shape having a third inner diameter smaller than the second outer diameter, the first adhesive tape having a first base material, the first base material having a first surface and a second surface opposed to the first surface, the first adhesive tape having a first adhesive layer provided on the first surface, the first adhesive tape being attached to the first substrate surface and the metal layer through the first adhesive layer; and a second adhesive tape having a fourth outer diameter smaller than the first outer diameter and larger than the
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: September 27, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yoshiharu Takada
  • Patent number: 11450830
    Abstract: A semiconductor device including a region arranged with a plurality of electrodes in a matrix, wherein the plurality of electrodes includes a plurality of first electrodes located along any one side of the region and a plurality of second electrodes located closer to the center of the region than the plurality of first electrodes, the first electrode and the second electrode have a different outline in a planar view, and the outline of the plurality of first electrodes includes a side having a zigzag shaped side or concave/convex shape.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 20, 2022
    Assignee: Japan Display Inc.
    Inventor: Kohei Kurata
  • Patent number: 11430729
    Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Lien Lin, Cheng-Te Lee, Rei-Lin Chu, Chii-Ming Wu, Yeur-Luen Tu, Chung-Yi Yu
  • Patent number: 11411032
    Abstract: An imaging device comprises a sensor substrate including a pixel array that includes at least a first pixel. The first pixel includes an avalanche photodiode including a light receiving region, a cathode, and an anode. The first pixel includes a wiring layer electrically connected to the cathode and arranged in the sensor substrate such that the wiring layer is in a path of incident light that exits the light receiving region.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: August 9, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Akira Tanaka, Yusuke Otake, Toshifumi Wakano
  • Patent number: 11404452
    Abstract: A manufacturing method of a display panel comprises: providing a first substrate; forming active switches on the first substrate; providing a second substrate disposed opposite to the first substrate; forming a color filter layer on the first substrate or the second substrate; and forming at least one spacer unit on the first substrate or the second substrate. The spacer unit comprises a photosensitive spacer material comprising two different wavelengths of light initiators.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 2, 2022
    Assignees: HKC CORPORATION LIMI TED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-Jen Chen
  • Patent number: 11404565
    Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 2, 2022
    Assignee: CAMBRIDGE ENTERPRISE LIMITED
    Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
  • Patent number: 11393906
    Abstract: A crystalline oxide semiconductor film with an enhanced electrical property is provided. By use of a mist CVD apparatus, a crystalline oxide semiconductor film with a corundum structure and a principal plane that is an a-plane or an m-plane was obtained on a crystalline substrate by atomizing a raw-material solution containing a dopant that is an n-type dopant to obtain atomized droplets, carrying the atomized droplets by carrier gas onto the crystalline substrate that is an a-plane corundum-structured crystalline substrate or an m-plane corundum-structured crystalline substrate placed in a film-formation chamber, and the atomized droplets were thermally reacted to form the crystalline oxide semiconductor film on the crystalline substrate.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 19, 2022
    Assignee: FLOSFIA INC.
    Inventors: Isao Takahashi, Takashi Shinohe, Rie Tokuda, Masaya Oda, Toshimi Hitora
  • Patent number: 11393801
    Abstract: A decoupling capacitor includes a first insulating layer extending in a horizontal direction, a storage plate arranged on the first insulating layer, a top plate facing the storage plate, a second insulating layer interposed between the storage plate and the top plate and having a plurality of through holes, a capacitor block including a plurality of capacitor structures in the plurality of through holes, a wiring structure covering the top plate, a first conductive pad arranged on the wiring structure and configured to be electrically connected to the storage plate through a first conductive path of the wiring structure, and a second conductive pad spaced apart from the first conductive pad in the horizontal direction in the same plane as the first conductive pad and configured to be electrically connected to the top plate through a second conductive path of the wiring structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunghun Shin, Jaejune Jang, Dukseo Park, Sunwoo Park, Howoo Park
  • Patent number: 11387214
    Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 12, 2022
    Assignee: INVENSAS LLC
    Inventors: Liang Wang, Rajesh Katkar
  • Patent number: 11380728
    Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing a semiconductor structure. The method includes forming photodetectors within a semiconductor substrate. A charge release layer is deposited over the semiconductor substrate. A conductive contact is formed over the charge release layer such that a contact protrusion of the conductive contact extends through the charge release layer. The charge release layer is disposed along opposing sidewalls of the conductive contact. The charge release layer is electrically coupled to ground via the conductive contact.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chung Su, Jiech-Fun Lu
  • Patent number: 11380755
    Abstract: Capacitors are disclosed. A capacitor includes a plate-to-plate capacitor and a finger-to-finger capacitor. The plate-to-plate capacitor includes at least a first plate and a second plate. The second plate is in proximity to the first plate. The finger to finger capacitor is in proximity to the first plate. The finger to finger capacitor includes a first plurality of finger elements and a second plurality of finger elements. The second plurality of finger elements is interleaved with the first plurality of finger elements. The first plurality of finger elements is electrically connected to the first plate and the second plurality of finger elements is electrically connected to the second plate. The second plurality of finger elements and the first plate form additional plate-to-plate capacitors.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Domagoj Siprak, Jonas Fritzin, Sundaravadanan Anantha Krishnan
  • Patent number: 11380711
    Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: July 5, 2022
    Inventors: Sohyeon Lee, Sungsu Moon, Jaeduk Lee, Ikhyung Joo
  • Patent number: 11373953
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first portion includes forming a first patterned conductive pad with a first through hole on a first interconnect structure over a first semiconductor substrate; patterning a dielectric material over the first interconnect structure to form a first patterned dielectric layer with a first opening that passes through a portion of the dielectric material formed inside the first through hole to accessibly expose the first interconnect structure; and forming a conductive material inside the first opening and in contact with the first interconnect structure to form a first conductive connector laterally isolated from the first patterned conductive pad by the first patterned dielectric layer. A singulation process is performed to cut off the first patterned dielectric layer, the first interconnect structure, and the first semiconductor substrate to form a continuous sidewall of a semiconductor structure.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11373943
    Abstract: A flip-chip film includes a substrate and a plurality of flip-chip film units. The plurality of flip-chip film units are disposed on the substrate, and each of the flip-chip film units includes a plurality of first metal traces arranged at intervals. A punch cut is defined between the first metal traces of two adjacent flip-chip film units.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: June 28, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yicheng Chen
  • Patent number: 11373970
    Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Anhao Cheng, Chun-Chang Liu, Sheng-Wei Yeh
  • Patent number: 11362029
    Abstract: An integrated circuit structure includes a first conductive plate, a second conductive plate, a plurality of conductive lines, and a plurality of conductive vias. The first conductive plate is disposed in a first layer on a semiconductor substrate. The second conductive plate is disposed in a second layer on the semiconductor substrate. The plurality of conductive lines are disposed in the first layer for surrounding the first conductive plate. The plurality of conductive vias are arranged to couple the plurality of conductive lines to the second conductive plate. The second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yi Chen, Yung-Chow Peng, Chung-Chieh Yang
  • Patent number: 11362046
    Abstract: Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Patent number: 11348843
    Abstract: A semiconductor device includes a field plate on an insulating film covering a transistor, the field plate being electrically coupled to a gate of the transistor via the insulating film, and the transistor being located on a substrate, a silicon nitride protective film covering the insulating film and the field plate, a silicon oxide base film on the silicon nitride protective film, and a MIM capacitor on the silicon oxide base film. The MIM capacitor includes a first electrode, a dielectric film and a second electrode which are stacked in an order. The MIM capacitor is formed by performing wet etching on the silicon oxide base film on the field plate after the dielectric film is formed.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 31, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Takuma Nakano, Tomoki Maruyama
  • Patent number: 11348947
    Abstract: The present disclosure discloses a manufacturing method for an array substrate and an array substrate. The method includes: forming a gate electrode, a gate insulating layer, a semiconductor layer, a source drain electrode layer and a photoresist layer on a substrate; patterning the photoresist layer to form a patterned photoresist layer; performing at least one wet etching on the source drain electrode layer and performing at least one dry etching on the semiconductor layer; performing an ashing processing between the steps of the wet etching and the dry etching. A ratio of a lateral etching rate to a longitudinal etching rate in the at least one ashing processing ranges from 1:0.9 to 1:1.5.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: May 31, 2022
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventors: En-tsung Cho, Yiqun Tian