Abstract: A diode and its fabrication method are provided. The diode includes a substrate, a buffer layer on a side of the substrate, a first film layer, a second film layer and a third film layer. The first film layer is a polycrystalline silicon film layer; the second film layer is an amorphous silicon film layer; and the third film layer is one of the polycrystalline silicon film layer and the amorphous silicon film layer. The diode at least includes a first portion, a second portion, a third portion, a first electrode, and a second electrode. The first portion is located in the first film layer; the second portion is located in the second film layer; and the third portion is located in the third film layer. The first electrode is electrically connected to the first portion, and the second electrode is electrically connected to the third portion.

Abstract: A wafer grinding apparatus performs grinding processing for grinding a semiconductor wafer with a grindstone. The grindstone has a wear rate as a characteristic. The wear rate is 5% or more, and less than 200%. A determination part performs determination processing for determining whether a grinding state with respect to the semiconductor wafer is abnormal or normal, based on at least one of a load current of a motor and a grinding wear amount.

Abstract: The lower surface of the wiring substrate includes a first region overlapping with the semiconductor chip mounted on the upper surface, and a second region surrounding the first region and not overlapping with the semiconductor chip. The first region includes a third region in which the plurality of external terminals is not arranged, and a fourth region surrounding the third region in which the plurality of external terminals is arranged. The plurality of external terminals includes a plurality of terminals arranged in the fourth region of the first region and a plurality of terminals arranged in the second region. The plurality of terminals includes a plurality of power supply terminals for supplying a power supply potential to the core circuit of the semiconductor chip, and a plurality of reference terminals for supplying a reference potential to the core circuit of the semiconductor chip.

Abstract: A self-light emitting display device comprises a circuit board including a driving thin-film transistor; a cathode; an organic film disposed between the circuit board and the cathode; an anode disposed between the circuit board and the organic film; and a color filter disposed between the circuit board and the anode and including a first color filter unit, a second color filter unit, and a third color filter unit; wherein the third color filter unit has a portion disposed between the first color filter unit and the second color filter unit, and wherein the third color filter unit is thicker than the first color filter unit and the second color filter unit.

Abstract: Semiconductor substrates and semiconductor devices produced from such substrates, such as photovoltaic (PV) cells, may exhibit toughened physical characteristics making them more suitable for use in mechanically challenging or stressful environments. Semiconductor substrates and semiconductor devices produced from such substrates, such as photovoltaic (PV) cells, may exhibit toughened thermal characteristics making them more suitable for use in environmentally challenging applications. Semiconductor substrates and semiconductor devices produced from such substrates, such as photovoltaic (PV) cells, may exhibit sufficiently toughened characteristics and increase impact resistance to permit packaging in non-rigid and light weight encapsulating layer(s). Semiconductor substrates and semiconductor devices produced from such substrates may exhibit sufficient flexibility to permit for rolling up during shipment and or for non-destructive deformation during deployment over uneven surfaces.

Abstract: A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed. The method includes a first process of forming an active region on a first main surface side of the semiconductor wafer and a second process of forming a first process control monitor (PCM) on a second main surface side of the semiconductor wafer. The method further includes before the second process, a third process of forming a second PCM on the first main surface side of the semiconductor wafer. The first PCM and the second PCM are formed at an area located at the same position in a plan view of the semiconductor wafer.

Abstract: A method for producing a CdTe solar cell is provided, wherein at least the following layers are deposited on a glass substrate within a vacuum chamber: a TCO layer acting as a frontal contact; at least one CdTe layer; a thin layer of a chlorine-containing compound, and an electrically conductive layer acting as a return contact. Here, a maximally 20 nm thick passivation layer made from CdS, in which chemically non-bound oxygen is embedded, is deposited on the TCO layer prior to deposition of at least one CdTe-layer.

Abstract: To provide a semiconductor device, wherein each of a transistor portion and a diode portion that are arrayed along an array direction has: a second-conductivity type base region provided above a first-conductivity type drift region inside a semiconductor substrate; a plurality of trench portions that penetrate the base region from an upper surface of the semiconductor substrate, extend at the upper surface of the semiconductor substrate and in a direction of extension perpendicular to the array direction, and have conductive portions provided therein; and a lower-surface side lifetime control region that lies on a lower-surface side in the semiconductor substrate, and from the transistor portion to the diode portion, and includes a lifetime killer. In the array direction, the transistor portion may have a portion provided with the lower-surface side lifetime control region, and another portion not provided with the lower-surface side lifetime control region.

Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

Abstract: A chip-mounted board including: micro light-emitting chips arranged in a matrix pattern in a light-emitting region; and a conductive line electrically connected to the micro light-emitting chips, the light-emitting region including a first region having a first luminance, a second region having a second luminance lower than the first luminance, and a third region having a third luminance lower than the first luminance and higher than the second luminance, the luminances being values determined with the same magnitude of current supplied to the micro light-emitting chips, the third region being positioned between the first region and the second region and satisfying the following formulas (1) and (2): (1+k)/(1?k)?63.895×tan(0.5°)×500/W+6.0525??(1) L2=k×L1??(2) wherein L1 represents the first luminance, L2 represents the second luminance, and W represents a width (unit: mm) of the third region.

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

Abstract: A semiconductor device includes first and second contact plugs in an insulating layer that is on a substrate, the first and second contact plugs spaced apart from each other. A spin-orbit torque (SOT) line on the insulating layer and overlapping the first and second contact plug is provided. A magnetic tunnel junction (MTJ) is on the SOT line. An upper electrode is on the MTJ. Each of the first and second contact plugs includes a recess region adjacent the SOT line. A sidewall of the recess region is substantially coplanar with a side surface of the SOT line and a side surface of the MTJ.

Abstract: A semiconductor memory includes a substrate and an alternating stack of first insulators and first conductors above the substrate. First to third regions are provided in this order along a direction parallel to a surface of the substrate. The alternating stack is in a dummy region at part of each of the first to third regions. Second and third conductors extend in parallel to each other in the direction above a top one of the first conductors. A plurality of first pillars extend through the second conductor. A plurality of second pillars extend through the third conductor. A columnar first contact is provided on the second conductor in the first region, and a columnar second contact is provided on the third conductor in the first region. The second and third conductors are separated from each other in the first and second regions, and connected to each other in the third region.

Abstract: An electronic circuit including a semiconductor substrate having first and second opposite surfaces and electrically-insulating trenches. Each trench includes at least first and second insulating portions made of a first insulating material, extending from the first surface to the second surface, first and second intermediate portions, extending from the first surface to the second surface, made of a first filling material, and a third insulating portion extending from the first surface to the second surface, the first insulating portion being in contact with the first intermediate portion, the second insulating portion being in contact with the second intermediate portion, and the third insulating portion being interposed between the intermediate portions.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.

Abstract: In an embodiment, a method includes: growing a phase change material on a platform configured for a semiconductor workpiece process; setting the phase change material to an amorphous state; performing the semiconductor workpiece process within a semiconductor processing chamber; and measuring resistance across two points along the phase change material.

Abstract: Provided is an integrated circuit including a semiconductor substrate, a plurality of gate lines and a plurality of metal lines. The plurality of gate lines are formed in a gate layer above the semiconductor substrate, where the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the second direction. The plurality of metal lines are formed in a conduction layer above the gate layer, where the plurality of metal lines are arranged in the first direction and extend in the second direction. 6N metal lines and 4N gate lines form a unit wiring structure where N is a positive integer and a plurality of unit wiring structures are arranged in the first direction. Design efficiency and performance of the integrated circuit are enhanced through the unit wiring structure.

Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.