Abstract: A programmable input/output cell (I/O cell) for use with integrated circuits, and in particular programmable logic devices, is presented comprising input receiver circuitry, output driver circuitry and programmable elements. The input receiver and output driver circuitry each include multiple receivers/drivers that provide an interface between the signaling level of the integrated circuit and at least two other signaling standards. The programmable elements may be programmed to select a different signaling standard for each I/O cell to operate at, if desired. For instance, adjacent I/O cells may be connected to two different bus structures that utilize different signaling levels. The invention enables one I/O cell to translate between the PLD signaling level and the first bus signaling level, while the second I/O cell translates between the integrated circuit signaling level and the second bus signaling level.

Abstract: The invention relates to a circuit of which the operating rate varies according to temperature, supply voltage and intrinsic quality of the transistors of the circuit, associated to a compensating circuit which comprises a constant current source (26) that produces a substantially constant current which is independent of temperature, supply voltage and intrinsic quality of the transistors of the circuit, a variable current source (28) producing a current that increases in an inverse proportion to temperature, supply voltage and intrinsic quality of the transistors of the circuit, and means for decreasing the operating rate of the circuit when the difference of the currents produced by the first and second sources increases.

Abstract: A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows.

Abstract: An input buffer is provided that converts a TTL logic signal to a CMOS logic signal and controls an CMOS output level while eliminating static current consumption even when an external bias voltage is changed. The input buffer improves a low-to-high input signal switching speed. Further, the input buffer can be used for low current and high-speed operation. The input buffer includes an inverter unit having pull-up and pull-down transistors with commonly coupled drains coupled between a power supply voltage and a ground voltage. The input buffer further can include a transistor control unit that receives an output signal of the input buffer to completely turn off the pull-up transistor when the TTL input signal is a high level and rapidly turn on the transistor when the TTL input signal is a low level.

Abstract: Disclosed is a switched capacitor type D/A converter, which comprises: an operational amplifier; a plurality of capacitors; a plurality of first switches which alternatively change connection thereof dependently on whether the filter is in an output mode or a reset mode so that the filter realizes an offset canceling function; a voltage source; and a second switch for directly connecting an output of said operational amplifier with said voltage source at a beginning of the reset mode.

Abstract: An input/output (I/O) buffer with reduced ring-back effect is provided. This I/O buffer is designed for a data transmission bus, such as a GTL+bus, for the transmission of a high-frequency and low-swing data signal. This I/O buffer is designed for the purpose of reducing the undesirable ring-back effect in the I/O buffer. The I/O buffer is characterized by the provision of a variable-resistance device that is connected between the system voltage and the input end of the I/O buffer. The system voltage is set to be equal in magnitude to the high-voltage logic state of the data signal received by the I/O buffer from the data transmission bus. When the input data signal is higher in magnitude than a preset reference voltage, i.e., at the high-voltage logic state, the variable-resistance device is switched to a low resistance value; on the other hand, when the data signal is lower in magnitude than the reference voltage, the variable-resistance device is switched to a near-infinity resistance value.

Abstract: A programmable buffer circuit comprises a logical gate circuit having a second input terminal, a third input terminal and a first output terminal, and a first input terminal. The second input terminal is connected to the first input terminal. Further, a selective signal generating circuit for supplying two kinds of selective signals in logical level to the third input terminal is provided. A tri-state inverter circuit having a fourth input terminal and a second output terminal is provided and a tri-state buffer circuit having a fifth input terminal and a third output terminal is provided. The fourth input terminal and the fifth input terminal are connected to the first output terminal. A fourth output terminal is connected to the second output terminal and the third output terminal.

Abstract: A logic circuit contains a first transistor with a logic signal supplied to the base and having its collector connected to an output node. A second transistor has a collector connected to the emitter of the first transistor and an emitter connected to a reference potential, in which the collector current supplied to the first transistor corresponds to the level of the control signal supplied to the base. A p-channel insulated gate field-effect transistor is connected between the power supply and the output node, and a first bias circuit supplies a bias voltage to the gate of the p-channel insulated gate field-effect transistor as the load. An n-channel insulated gate field-effect transistor is connected between the power supply and the output node and parallel to the p-channel insulated gate field-effect transistor as the load, and a second bias circuit supplies a bias voltage to the gate of the n-channel insulated gate field-effect transistor.

Abstract: A programmable logic device architecture incorporating a cross-bar switch is disclosed. In a preferred embodiment, a plurality of logic cells is programmably interconnected to form an array of logic cells capable of implementing complex logic functions. A user selectable cross-bar switch block having dedicated programmable connectors is coupled to the array of logic cells by way of a mode control circuit switch. The mode control circuit switch is arranged to couple the dedicated cross-bar switch block to the array of logic cells in a first mode and to de-couple the cross-bar switch block from the array of logic blocks in a second mode.

Abstract: A level shifter, irrespective of a variation of a threshold voltage, is capable of changing input signals of 0 volt and 5 volts to the signals of -10 volts and 10 volts, respectively, without using an additional voltage and an inverted signal even when a threshold voltage of an NMOS transistor is 4 volts. The level shifter includes a voltage distributor, e.g., two level output inverter generates a driving signal for an NMOS transistor and a PMOS transistor irrespective of a threshold voltage variation with respect to input voltages of 0 volts and 5 volts. A two level input inverter drives the PMOS transistor and NMOS transistor in response to a driving signal from the two level output inverter and outputs a signal, the level of which is reduced as much as a threshold voltage at voltages of -10 volts and 10 volts. An inverter outputs the output signals from the two level input inverter as voltage signals of -10 volts and 10 volts.

Abstract: Described is a user-controlled, variable-delay interconnect structure for a programmable logic device (PLD), and a method for using this structure. In accordance with the invention, the signal propagation delays for selected signal paths can be precisely adjusted either while the PLD is being programmed or while the PLD is operating as a logic device. The delays are adjusted by selectively connecting otherwise unused interconnect lines to the signal path to increase the capacitive load on the interconnect lines that define the signal path. The ability to control the load on selected signal paths advantageously enables a user to precisely match the signal propagation delays of two or more signal paths. In one embodiment, the loads of selected signal paths can be modified while the FPGA is operational.

Abstract: The input and output interface in the present invention can includes following components. A first circuit and a second circuit are placed. Means for switching a coupling between the two circuits is used. Grounding means is employed for setting the first terminal to a ground connection. Triggering means is used for triggering the grounding means and the switching means. The method for interfacing input and output between a first circuit and a second circuit includes the steps as follows. At first, an output disable signal of the first circuit is detected. Then a first terminal is isolated from a second terminal. The first terminal is an input and output terminal of the first circuit and the second terminal is an input and output terminal of the second circuit. Next, the first terminal is grounded. The first terminal is then floated. Finally, the first terminal and the second terminal is coupled for the first circuit to receive an output signal from the second circuit.

Abstract: A method of compressing data involves receiving a symbol, and a subsequent symbol; determining in a compression dictionary whether the symbol has a valid extension pointer; using, in the event the symbol does have a valid extension pointer, the valid extension pointer to access string extension symbols; determining, in the event the symbol does have a valid extension pointer, whether the string extension symbols equal the at least one subsequent symbol; determining in the compression dictionary, in the event the string extension symbols do not equal the at least one subsequent symbol, whether the symbol has a valid parallel extension; repeating, in the event the symbol has a valid parallel extension, the using step; repeating, in the event the string extension symbols do not equal the at least one subsequent symbol, the determining of whether the symbol has a valid extension pointer; inserting, in the event the symbol does not have a valid extension pointer or in the event the symbol does not have a valid par