Abstract: Variable length data (e.g., for hospital patients) is embedded in a B-tree type index structure of a relational data base. A logically related inverted B-tree index is used to access the original index. Access time, and storage space for the inverted lists, are decreased by data compression techniques and by encoding certain inverted list parameters in sparse array bit maps.

Abstract: A digital control device is used with a character generator for producing text in a typescript having multiform characters, such as Arabic script. The character generator includes a character store with a base page section to store codes identifying the base body of the characters and at least one additional page section to store codes identifying special character forms. The control device is arranged to register and process the incoming character identification codes to produce a control signal having a first state to enable a final address code to be produced to address the base page section in the character store and having a second state to enable a final address code to be produced to address the additional page section in the character store.

Abstract: A code track on a rotable member (e.g., a disc) defines a pseudo-random sequence of binary digits consisting of ones and noughts. The pseudo-random sequence extends continuously around the rotatable member and includes a given number of n consecutive noughts. The binary digits of the sequence are arranged so that each group of n adjacent digits is different from each other group of n adjacent in the pseudo-random sequence. A reading mechanism is operatively positioned relative to the code track for reading n consecutive digits of the pseudo-random sequence, wherein each n consecutive digits of the pseudo-random sequence define a position of the rotatable member.

Abstract: In a data processing system for use in accessing a main memory from each of a central processing unit and a channel unit through a common data bus, an address translation circuit is incorporated in the central processing unit so as to translate each logical address into a real address physically allotted to the main memory and is used in common by the central processing unit and the channel unit. Address translation is carried out by the address translation circuit selectively for the central processing unit and the channel unit. When the main memory is accessed from the channel unit through the central processing unit, an indication signal is delivered from the main memory only to the central processing unit to indicate either reception or supply of a data group. The central processing unit energizes the channel unit to assign the data bus to the channel unit. Thereafter, the data group is transferred between the main memory and the channel unit through the data bus.

Abstract: A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers.

Abstract: Apparatus (100) and a method (5) are used for polling asynchronous sensors (1, 2, 3) of a computer system to optimize the data load offered by the sensors to a central processor (4). The polling apparatus and method operate in accordance with time delay status (4200, 4210, 4220) recorded in the sensor buffer stores (420, 421, 422) of the memory unit (42) of the central processor. The system determines the amount of data received in a sensor buffer store during the polling sequence and dynamically varies the value of the time delay status to optimize the load of sensor data offered the central processor.

Abstract: Standard ASCII coded text is divided into alpha, numeric, and punctuation tokens. Each token is converted to a string of four-bit nibbles. One nibble is coded to identify the type of token. Additional nibbles are coded to identify the location, if any, of a corresponding alpha or punctuation token in a global dictionary. If no corresponding alpha token is in the dictionary, an alpha token is divided into prefixed, suffixes, and a stem. The location of any prefixes in a table of prefixes, suffixes in a table of suffixes, and the number, and location of corresponding individual characters in a table, of the remaining stem are then coded and stored as part of the string of four-bit nibbles for the alpha tokens. Numeric tokens are stored as a string of four-bit nibbles in which the first nibble identifies the type of token, the next nibble the length, followed by a nibble for each of the digits.

Abstract: In a sort circuit comprised of m sort stages, the sort stages perform respective sorts, in parallel, on each input word as it is received. In particular, in the j.sup.th one of the stages, j=1,2, . . . m, a bit is associated with each different possible pattern of the values of the D.sub.j highest-order digits in the input word, D.sub.1 >D.sub.2 > . . . D.sub.m. As each input word is received, the values of its D.sub.j higher-order digits are examined and the associated bit is set.During output processing, the j.sup.th stage of the sort circuit receives from the (j+1).sup.st stage a D.sub.j+1 -digit pattern representing the D.sub.j+1 highest-order digits of a word or words previously input to the sort circuit. The D.sub.j+1 -digit pattern is used to identify the bits within the j.sup.th stage associated with the D.sub.j -digit patterns whose D.sub.j+1 highest-order digits match the input pattern. The bits thus identified are processed within the j.sup.

Abstract: An electronic language interpreter is operated such that an uninflected word is entered to obtain at least one inflected form of that word. The interpreter comprises three types of memories. The first contains a plurality of words of the uninflected form inclusive in their uninflected word. The second contains a plurality of words in a second language each of which is equivalent to one of the words within the first memory. The third memory contains digital data reflecting a certain number of inflection principles used to inflect the inflected words stored in the first memory. An alphabetical keyboard is provided for entering the uninflected form of the word. An inflection selection keyboard is provided for entering desired inflection information that is used to select data reflecting the appropriate inflection principles stored digitally in the third memory.

Abstract: A vending machine stores a plurality of video game programs which may be selected for purchase. The game program is transferred to a programmable cartridge which the user inserts into the machine. The programmable cartridge is then removed for use on a separate video game unit. The programmable cartridge includes a use interval circuit which is preset by the vending machine to expire after a time interval. When expired, the transferred program is rendered inoperable.

Abstract: A full floating point vector processor includes a master processing unit having DMA I/O means, a wide bandwidth data memory having static RAM and/or interleaved dynamic RAM, an address generator operative to provide address generation for data loaded in the data memory, a concurrently operating pipeline control sequencer operative to provide fully programmable horizontal format microinstructions synchronously with the addresses generated by the address generator, and a pipelined arithmetic and logical unit responsive to the addressed data and to the synchronously provided microinstructions and operative to evaluate one of a user selectable plurality of computationally intensive functions. The address generator, the pipeline controlsequencer, and the master processing unit are configured in parallel. The address generator includes means operative to provide pipeline input and output data dependent address generation.

Abstract: An automatic syntax analyzing method is applied to a natural language processing system. It includes the step of detecting by dictionary consultation the syntactic category of words forming an inputted sentence and steps of assumptively applying, when the input sentence includes at least a word unregistered in the dictionary section, an adequate category which satisfies a predetermined grammatical regulation of the input sentence to the unregistered word independent of the dictionary consultation.

Abstract: A memory data coincidence device includes a volatile read write memory connected to a main power source and auxiliary backup power source, and a keyboard for supplying data to the read write memory. The device further includes a read only memory for storing all data capable of being stored in the read write memory and a central processor unit (CPU) which compares the data of the read write memory with all data of the read only memory before it reads data out of the read write memory. If no coincidence takes place, the CPU sends forth a signal denoting the condition that the read write memory is not backed up.

Abstract: Automated spelling correction converts, by prescribed linguistic procedures, each word to be corrected to a skeleton, and compares that skeleton with a data base of skeletons derived by identical linguistic procedures from a dictionary of correctly spelled words. In the event of a match between the two skeletal terms, the correctly spelled word (or words) associated with the matched skeleton is presented for replacement of the misspelled word. In the event the comparison does not yield a correct match, the skeletal form of the misspelled word is repeatedly modified and each modified form is compared with the data base of skeletons.

Abstract: An information output system includes a display unit and a printer for visibly outputting data has a control unit for controlling these units. In each display unit or printer, the outputted data is controlled by an arbitrary mode among a plurality of predetermined modes concerning the data display format. For this purpose, the control unit includes a rewritable table for specifying the number of data to be outputted, i.e., the picture size for each unit. If a picture size mode is specified corresponding to a unit, that unit visibly outputs the data according to its picture size mode. Also, in the case where the contents displayed on a display unit are to be printed on a printer to yield a hard copy, it is possible to print the contents with the picture size mode of the printer matched to that of the display unit by referencing the rewritable table.

Abstract: A peripheral processor has an architecture wherein the function controlling information of a program is separated from portions of the sequence of execution controlling information and each are stored in the form of tables. The function controlling information takes the form of a table including a plurality of function specifying entries. The function execution sequence controlling information takes the form of a table of pointers. In this invention, function controlling entries, each having a plurality of fields for defining, modifying, and specifying the functions and related data to be executed, need not be repetitively duplicated throughout the program. Instead, the shorter pointers to the function table entries can be provided in the sequence table in the sequence in which the functions are to be executed.

Abstract: A method of performing a sequence of related activities in multiple digital processors includes the steps of: executing a portion of a first activity of the sequence in a first processor and then executing an INTERPROCESSOR CALL instruction to a second activity in a second processor; suspending execution of the first activity in response to the CALL and signaling the second processor that the second activity has been called by the first activity; completely executing the second activity in the second processor and then executing an INTERPROCESSOR NEXT instruction to a third activity in a third processor; signaling the third processor in response to the NEXT instruction that the third activity has been called not by the second activity but by the caller of the second activity; and completely executing the third activity in the third processor and, upon completion thereof, signaling the third activity's caller to resume execution of the suspended activity.

Abstract: A cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the cache are equal in capacity. The two parts of the cache, designated I-Cache and O-Cache, are semi-independent in their operation and include arrangements for effecting synchronized searches, they can accommodate up to three separate operations substantially simultaneously. Each cache unit has a directory and a data array with the directory and data array being separately addressable. Each cache unit may be subjected to a primary and to one or more secondary concurrent uses with the secondary uses prioritized.