Abstract: A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through an input latch circuit by a feedback reset signal, such that commands are pipelined for three latency operation. In response to the command signals, the two latency control circuit produces a set of control signals according to a two latency algorithm. In response to the same command signals, the three latency control circuit independently produces a set of three latency control signals according to a three latency algorithm. In two latency operation, access time for signal development is externally controlled, while in three latency operation access time is internally controlled. In three latency operation, signal development time is determined separately for reads and writes.

Abstract: A method and apparatus are provided for parallel addressing a CAM and a RAM, and also for using a single wordline to address the CAM and/or RAM. The CAM and RAM are addressed using a common wordline, and the common wordline is also used for writing to the CAM during a write cycle and strobing the CAM during a read cycle.

Abstract: A method and circuit programs and automatically verifies the programming of selected EEPROM cells without alternating between programming and reading modes like prior art methods and circuitry. The circuitry includes a programming circuit and a bit line voltage regulation circuit. The programming circuit further includes a novel sense amplifier which unlike prior art sense amplifiers, is operable during both cell reading and programming modes. Included in the sense amplifier are two current providing circuits. A first circuit provides current to a selected EEPROM cell which is sufficient for reading the programmed state of the cell, and a second circuit which automatically provides additional current when required, for programming the cell. The sense amplifier detects when programming of a selected EEPROM cell has completed and causes programming of that cell to be terminated. The voltage regulation circuitry regulates the bit line voltage to the selected EEPROM cell's drain electrode.

Abstract: A memory device is disclosed which includes memory cells having m possible states, where m is at least 2. The memory device includes a multiplexed pair of output paths, wherein each output path is coupled to sense the state of a memory cell and includes a read path circuit, a column load circuit, and a comparator. Provided between the pair of output paths is a switching circuit for coupling the comparators to one another in response to a control signal. For single-bit read operations, each output path senses and outputs the data of the associated memory cell, and the control signal is inactive. When the control signal is active, the read path circuit and column load circuit of one of the output paths is disabled and the switching circuit couples the other read path circuit to the second comparator such that the state of the memory cell is sensed by two comparators.

Abstract: A novel method of connecting and operating an NVM transistor in the switching circuit is provided. A full voltage signal can be switched across an NVM transistor. The device is turned on prior to the signal switching and the electrical characteristics of the NVM device relative to the associated circuitry is carefully regulated to prevent the source-drain voltage from rising above a preselected maximum voltage (e.g. 1 v). Two embodiments of the present invention are described. In the first embodiment, the relative impedances of the NVM transistor and its driving circuit are controlled. The driver circuit and the NVM transistor switch act as a resistor divider circuit with a percentage of the full switching voltage appearing across the NVM transistor and the driver circuit according to their relative impedances. The second embodiment is applicable when the NVM transistor switch drives a capacitive load. The rise time of the signal to be switched is controlled.

Abstract: A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

Abstract: A dynamic random access memory (DRAM) device that is selectively operable in a normal write mode, in a block write mode, or in a blocked flash write mode in accordance with a mode select signal. In the preferred embodiment, each column of a 512.times.512 DRAM is divided into eight superblocks of 64 columns, each superblock being in turn divided into eight blocks of 8 columns each. An address decoder decodes the most significant column address bits A8-A6 to provide a group select signal specifying a 64-bit superblock, the next most significant column address bits A5-A3 to provide a block select signal specifying a 8-bit block, and the least significant column address bits A2-A0 to provide a cell select signal specifying a particular column. In the normal write mode, data is written to the specified column in the specified block in the specified superblock. In the block write mode, the same data is simultaneously written to selected columns in the specified block in the specified superblock.

Abstract: A row decoding circuit for an EEPROM is described. The row decoding circuit includes a first circuit and a second circuit. The first circuit delivers to a word line a predetermined dc voltage in response to a decode signal during both read operation and write operation and stops delivering the predetermined dc voltage when the word line is selected during erase operation. The predetermined dc voltage is the read voltage when the word line is selected during read operation, is the write voltage when the word line is selected during write operation and is a prescribed voltage level when the word line is not selected during either read operation or write operation. The second circuit delivers to the word line a negative erasure voltage in response to the decode signal when the word line is selected during erase operation and stops delivering any voltage to the word line when the word line is not selected during erase operation.

Abstract: A memory circuit for use with a spatial light modulator having an array of electrically addressable, micro-mechanical, modulating elements, whose address electrodes determine how that element will affect incident light. The memory circuit has at least one static memory cell in communication with the address electrodes of each modulating element. Each memory cell receives data for determining its micro-mechanical movement via a bit-line down each column of memory cells. A row select signal determines whether the data will be written to that row. A two-level voltage line supplies power to each memory cell, with one level being used for writing to the cell and another level being used for operating the modulating element.

Abstract: A semiconductor integrated circuit device having a high-efficiency transfer gate and which is applicable to a DRAM which has voltage-raised word lines configured from a data retention node, a data line that is precharged to a required level, a MOS transistor with the source and the drain each connected to a data line and a data retention node, a sense amplifier that amplifies the data that has been transferred to the data line via this MOS transistor a step-up circuit that applies a voltage that is higher than the drain voltage when compared with an absolute value, to the gate of the MOS transistor, and a step-down circuit for reducing the absolute value of a gate voltage of the MOS transistor at the timing of activation of the sense amplifier.

Abstract: A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and are furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistors are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, such as an EPROM cell, as compared to reading circuits previously used.

Abstract: In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordlines for activating individual memory devices joined to each bitline, apparatus for providing constant current in the conducting state of a memory device connected to a bitline, a device connecting a source voltage to a plurality of bitlines, and a reference bitline for providing an output reference signal, the improvement including apparatus for providing a source of current in addition to current through the device connecting a source voltage to a plurality of bitlines in order to charge any capacitance of a selected bitline when that bitline is selected whereby switching between memory devices joined to different bitlines is accelerated.

Abstract: There is a provided non-volatile semiconductor memory device including a memory cell including a source, a drain, a floating gate, and a control gate. To read out data from the memory cell, a voltage of not more than 2 V, obtained by decreasing an external power source voltage, is applied to the drain of the memory cell. Various constants of the memory cell are set so as to control an ON current to be not more than 300 .mu.A when the memory cell is placed in an ON state while a threshold voltage of the memory cell is low.

Abstract: A small ladder-type electric filter for use in radio equipment or the like, includes a casing, a plurality of resonators having a small mechanical quality coefficient and a frequency constant, and a plurality of resonators having a large mechanical quality coefficient. The small mechanical quality coefficient resonators and the large mechanical quality coefficient resonators being combined in series-parallel to each other. The external size of the large mechanical quality coefficient resonators is substantially equal to the external size of the small mechanical quality coefficient resonators. A plurality of terminal plates hold the plurality of small and large mechanical quality coefficient resonators in the casing. Slits are selectively formed in side edges of each of the plurality of large mechanical quality coefficient resonators for adjusting the resonance frequency of the large mechanical quality coefficient resonators to a predetermined resonance frequency.