Abstract: An aspect includes pruning a design space when generating a maximum power stressmark. A multi-stage design space search process is performed. Each stage includes calculating a number of instructions per cycle (IPC) for each instruction sequence in a set of instruction sequences that place a power stress on a system under analysis, removing one or more of the instruction sequences having an IPC lower than a pruning threshold from the set, evaluating at least one power metric of the remaining instruction sequences in the set, removing one or more of the instruction sequences having at least one power metric evaluated outside of one or more pruning ranges from the set, and passing the remaining instruction sequences in the set to a next stage. A maximum power stressmark is generated based on the evaluating of the at least one power metric from a final stage.

Abstract: One disclosed method includes communicating with a kernel running on a primary processor, by a second processor, in response to detection of a state change; performing a hardware operation, in response to the state change, using the kernel without waking user space on the primary processor, where the user space remains suspended; and resuming a sleep mode of the primary processor by suspending the kernel after the hardware operation is completed. One example of a hardware operation is modification of display data on a touchscreen display. The method of operation may perform the hardware operation using the kernel without waking hardware drivers other than a hardware driver related to the hardware operation.

Abstract: An aspect includes pruning a design space when generating a maximum power stressmark. A multi-stage design space search process is performed. Each stage includes calculating a number of instructions per cycle (IPC) for each instruction sequence in a set of instruction sequences that place a power stress on a system under analysis, removing one or more of the instruction sequences having an IPC lower than a pruning threshold from the set, evaluating at least one power metric of the remaining instruction sequences in the set, removing one or more of the instruction sequences having at least one power metric evaluated outside of one or more pruning ranges from the set, and passing the remaining instruction sequences in the set to a next stage. A maximum power stressmark is generated based on the evaluating of the at least one power metric from a final stage.

Abstract: A clock synchronizer adapted to synchronize reading a Timer that is clocked asynchronously to the system clock.

Abstract: A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.

Abstract: An electronic device having a pin for setting its mode of operation, wherein the pin is connected or connectable to a first connection of a resistor, wherein the electronic device is arranged to detect a location of the resistor, wherein the electronic device is arranged to detect a size of the resistor, wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and wherein the electronic device is arranged to determine a second setting based on the size of the resistor.

Abstract: An electronic device that requires setup of plural setting items upon initial startup operations includes a storage unit that stores designated setting information and setting status information indicating whether the setting items have been set up, which designated setting information and setting status information are stored and updated each time the setup of one of the setting items is completed; and a startup processing unit that refers to the storage unit upon performing startup operations to determine whether at least one of the setting items has been set up and starts setup operations for the setting items that have not yet been set up.

Abstract: A power supply includes a plurality of electronic components including one or more of a rectifier and a switching transistor, an input port configured to receive electrical energy from a power source and a circuit board comprising a cavity. At least one of the rectifier and the switching transistor is embedded in the cavity. The cavity is arranged proximal to the input port such that at least a portion of thermal energy generated by one or more of the rectifier and the switching transistor is dissipated from the power supply by way of the input port.

Abstract: A system on chip includes a debugging controller, a plurality of clusters, and a power management unit (PMU). The debugging controller is included in a first power domain and a joint test action group (JTAG) interface is included in the first power domain. Each of the clusters is included in at least second power domain different from the first power domain. The PMU is configured to release a powered-off state of the debugging controller in response to a debugging request signal output from the JTAG interface.

Abstract: Example embodiments disclosed herein relate to implementing a power down state in a computing device. A sleep command is issued to place a computing device in a sleep state in response to receipt of a power off command at the computing device. Content of memory of the computing device is written to non-volatile storage of the computing device and the computing device is placed in a power off state.

Abstract: Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.

Abstract: Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.

Abstract: Performance management methods for an electronic device with multiple central processing units (CPUs) are provided. First, thread loading rearrangement and CPU frequency evaluation are performed to obtain a plurality of evaluated performance values for different amounts of CPUs, wherein the plurality of evaluated performance values are relevant to power consumption values of the multiple CPUs. It is then determined whether to adjust an amount of used CPUs based on the plurality of evaluated performance values corresponding to the different amounts of CPUs.

Abstract: A method includes supplying power to a physical server from a plurality of power supplies, wherein operation of all hardware components of the server requires more power than any one of the power supplies can provide. A plurality of jobs are run on the server while the plurality of power supplies are supplying power to the physical server. The method further comprises identifying an amount of power required by each of the components, and identifying one or more components that are not required by one or more of the jobs that are running on the server. The method detects a loss of power from one of the power supplies and then selectively removes power from hardware components identified as not required so that at least a central processing unit and a memory device can continue running at least one job using power available from the operational power supplies.

Abstract: A computer system includes a power supply unit (PSU), a matching circuit, and a chip. The matching circuit includes a voltage conversion unit, a voltage-dividing unit, a first resistor, a comparator, a diode, and a delay unit. The comparator includes a non-inverting terminal electrically coupled to the PSU to receive a power-good signal, an inverting terminal electrically coupled to the voltage-dividing unit to receive a reference voltage, and an output terminal. The delay unit is electrically coupled to a power supply and a power-good signal pin of the chip. When a voltage of the power-good signal is greater than the reference voltage, the output terminal of the comparator outputs a high level signal, the diode is turned off and the power supply is delayed by the delay unit and then output to the power-good signal pin of the chip.

Abstract: There is provided a power supply device having a primary side on which a primary winding of a transformer is located and a secondary side on which a secondary winding of the transformer is located, and supplying power to a load, the device including: a photo coupler transmitting load short-circuit information from the secondary side to the primary side, a standby power supply terminal supplying power to the photo coupler; and a current passing unit connecting the photo coupler to the load.

Abstract: In one embodiment, a power supply controller may be formed including configuring the power supply controller to use an error signal and a ramp signal to control a duty cycle of a switching control signal that is configured to control first and second switches to charge a battery, and configuring the power supply controller to selectively offset a dc value of the ramp signal responsively to detecting the adapter current is greater than a first value wherein offsetting the dc value of the ramp signal changes the duty cycle of the switching control signal to supply current from the battery to a load.