Abstract: Delivery of energy by a defibrillator or other medical device is inhibited when the processor or software that controls a module of the medical device operates abnormally. A windowed watchdog timer (WWDT) incorporated into one module of the medical device is used to control the operation of other modules of the medical device via a software-based extension technique. As a result, the risk of harm to the patient is reduced compared to medical devices that incorporate over-limit type watchdog timers. In addition, costs associated with implementing WWDTs in multiple modules of the defibrillator are avoided, thereby lowering the overall cost of implementation.

Abstract: A network including a plurality of interconnecting devices, each of which interconnects communication between two transmission media and has a disconnect function for disconnecting communication to one transmission medium in a case where communication from the other transmission medium has been disconnected, is managed by storing interconnecting device information that identifies one or more of the interconnecting devices having a disconnection release function for releasing operation of the disconnect function.

Abstract: An multimedia synchronization services system has been provided that can synchronize input actions and test data measurements associated with activities of a client/server computer system. The system can be applied to virtual test systems coupled to a contact center to provide time latency measurements between input actions to the calling center and resulting contact center functions.

Abstract: A debugging apparatus includes: a processor core operated by a program stored in a program memory to read a data stored in a data memory or write a data; a debugger controller for performing a debugging on the processor core upon receipt of a command from a host computer and outputting a data break point address; and a memory break controller for observing an address of a data memory used by the processor core, recognizing an address as a break point address to output a break signal to the debugger controller and the processor core to suspend the operation of the processor core, when the address is sensed to be identical, and transmitting a corresponding address and data to the host computer through the debugger controller. Since an address and a data of a specific data memory are monitored to recognize a data flow and change of the specific address, an error that an erroneous calculation is inputted a during processing or a data memory is erroneously assigned is quickly sensed.

Abstract: This invention is comprised of a data processing system containing at least one main processor connected to a system bus, a system memory connected to the system bus and accessible to each of the main processors, a tamper mechanism, and a local service processor. The tamper mechanism is configured to change state each time the system is inserted into a slot in a rack enclosure. The local service processor is connected to the tamper mechanism and configured to update an insertion log upon detecting a change in state of the tamper mechanism. The insertion log provides a count and a history of rack insertions to which the system has been subjected. The system may include a non-volatile storage element which is updated exclusively by the local service processor that contains the insertion log. The insertion log may include an insertion counter. In this embodiment, the local service processor is configured to increment the insertion counter upon each insertion.