Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor with a high full well capacity (FWC). A first integrated circuit (IC) chip and a second IC chip are stacked with each other. The first IC chip comprises a first semiconductor substrate, and the second IC chip comprises a second semiconductor substrate. A pixel sensor is in and spans the first and second IC chips. The pixel sensor comprises a transfer transistor and a pinned photodiode adjoining the transfer transistor at the first semiconductor substrate, and further comprises a plurality of additional transistors (e.g., a reset transistor, a source-follower transistor, etc.) at the second semiconductor substrate. A bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other and are configured to be biased with different voltages (e.g., a negative voltage and ground).

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a nanostructure, an isolation structure, an isolation fin, and a gate stack. The method includes turning the substrate upside down and removing the base to expose the isolation structure. The method includes partially removing the isolation structure to form a first trench in the isolation structure. The first trench exposes a portion of the isolation fin. The method includes removing the portion of the isolation fin through the first trench to form a second trench in the gate stack. The method includes partially removing the gate stack through the first trench and the second trench. The second trench passes through the gate stack and divides the gate stack into a first part and a second part.

Abstract: There is provided a display device including a base substrate, a conductive connection layer on the base substrate, a partitioning wall on the conductive connection layer, and a light emitting element on the conductive connection layer and in a space surrounded by the partitioning wall in a plan view, wherein the conductive connection layer includes a first portion overlapping the partitioning wall and the light emitting element, and a second portion not overlapping the partitioning wall and the light emitting element, an electrical conductivity of the first portion being greater than an electrical conductivity of the second portion.

Abstract: A semiconductor device includes a first electrode, a first semiconductor layer of a first conductivity type on the first electrode, a first pillar of a second conductivity type on the first semiconductor layer, the first pillar having a first average concentration of impurities, a second pillar of the first conductivity type on the first semiconductor layer, and including a first layer having a second average concentration of impurities lower than the first average concentration, and a second layer having a third average concentration of impurities higher than the first average concentration, a second semiconductor layer of the second conductivity type on the second pillar, a third semiconductor layer of the first conductivity type on the second semiconductor layer, a second electrode connected to the first pillar and the third semiconductor layer, a third electrode, and an insulating film disposed between the second semiconductor layer and the third electrode.

Abstract: A semiconductor device includes a substrate, at least one finFET on a first area of the substrate, the at least one finFET including a first gate structure and first source/drain regions on opposite sides of the first gate structure, and a planar FET on a second area of the substrate, the planar FET including a second gate structure and second source/drain regions on opposite sides of the second gate structure, wherein the first gate structure includes a first gate insulating layer, a first metal gate, and first spacers, the second gate structure includes a second gate insulating layer, a second metal gate, and second spacers, wherein the upper surfaces of the fin and the substrate are at a same height, and wherein the second gate insulating layer includes a first oxide layer in a recess of the substrate and a second oxide layer on the first oxide layer.

Abstract: Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from the memory-array region into a stair-step region. Individual stairs in the stair-step region comprise one of the conductive tiers. Conductive vias are individually directly against conducting material that is in the one conductive tier in one of the individual stairs. Insulator material in the stair-step region is directly above the stairs. An insulative-material lining is circumferentially around and extends elevationally along individual of the conductive vias between the individual conductive vias and the insulator material.

Abstract: The present disclosure discloses a semiconductor device comprising a plurality of epitaxial layers including a barrier layer and a channel layer such that two-dimensional carrier densities are formed at an interface of the barrier layer and the channel layer, wherein a priority of charge carriers of the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer can be changed by applying an electric field across the barrier layer. The semiconductor device further comprises a first source terminal and a second source terminal, wherein in one of the first source terminal and the second source terminal is ohmic to electrons and other one is ohmic to holes. The semiconductor device further comprises a first drain terminal and a second drain terminal, a gate terminal, and a set terminal ohmic to the channel layer.

Abstract: This application discloses a method for making an elevated source-drain structure of a PMOS in an FDSOI process, including: Step 1, forming a gate structure of a PMOS on an FDSOI substrate; Step 2, forming an elevated source-drain structure, further including: Step 21, forming a seed layer; Step 22, forming a bulk layer, the bulk layer being a B—Ge-doped Si epitaxial layer. Step 23, forming a first cap layer and a second cap layer in sequence, the first cap layer being a B-doped Si epitaxial layer, the second cap layer being a Si epitaxial layer; Step 24, performing a thermal oxidation process to form a top oxide layer and diffuse B impurities from the first cap layer into the bulk layer, the seed layer and the bottom semiconductor substrate; Step 25, removing the top oxide layer; and Step 26, forming a third cap layer.

Abstract: A semiconductor storage device according to an embodiment includes a multi-layered body, a first dividing part, a second dividing part, a third dividing part, second columnar bodies, and third columnar bodies. The third dividing part is between the first dividing part and the second dividing part. The third dividing part divides each of gate electrode layers. The third dividing part includes first columnar bodies. The first columnar bodies having insulating properties at least in outer circumferential portions of the first columnar bodies. A width of each of the first columnar bodies is larger than a distance between two second columnar bodies adjacent in a second direction included in the second columnar bodies or larger than a distance between two third columnar bodies adjacent in the second direction included in the third columnar bodies.

Abstract: Disclosed are a crystalline p-type semiconductor film having a plurality of crystal grains with an average grain size of submicron and including a tin-doped copper halide, and a semiconductor device, a thin film transistor, a diode, and an electronic device including the same.

Abstract: A light emitting diode structure comprising: a p-type region; an n-type region; a light emitting region for recombination of carriers injectable by the p-type region and the n-type region; and a via passing through the light emitting region, wherein the via defines the perimeter of a light emitting surface of at least one pixel and comprises a material configured to enable injection of carriers into the p-type region or the n-type region, wherein one of the p-type region and n-type region is configured such that carriers generated in the one of the p-type region and the n-type region diffuses through the other one of the n-type region and the p-type region prior to recombination in the light emitting region.

Abstract: An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.